处理器微架构：实现视角

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"Processor Microarchitecture: An Implementation Perspective" 是一本关于计算机处理器微架构的书籍，由Antonio González, Fernando Latorre和Grigorios Magklis撰写，于2011年出版。这本书深入探讨了处理器设计的实现层面，为读者提供了关于如何设计、分析和优化处理器微架构的专业知识。处理器微架构是计算机科学中的核心概念，它涉及到CPU内部的组织结构和工作原理。在本书中，作者可能涵盖了以下关键知识点： 1. **指令集架构（ISA）**：处理器微架构的基础是其指令集，它定义了处理器可以执行的指令类型。ISA决定了处理器能够处理的计算任务的范围和效率。 2. **数据路径与控制逻辑**：处理器内部的数据流动路径和控制单元的运作机制，包括ALU（算术逻辑单元）、寄存器、控制信号等。 3. **缓存系统**：高速缓存（Cache）是提高处理器性能的关键，书中可能详细讨论了不同级别的缓存（如L1, L2, L3），缓存的替换策略和一致性问题。 4. **多核与并行处理**：随着技术的发展，多核处理器成为主流，书中可能涉及了多核架构的设计，以及并行计算的概念和挑战。 5. **内存层次结构**：从寄存器到主存，处理器如何管理这个复杂层次的内存系统，包括存储器访问时间、带宽和一致性协议。 6. **微操作（Microoperations）和微码**：微操作是处理器执行高级指令时分解出的低级别操作，微码则用于控制这些操作，书中可能介绍了它们在复杂指令集中的作用。 7. **流水线技术**：流水线技术通过将处理过程划分为多个阶段来提高效率，书中可能会讨论流水线的各种类型（如深度流水线、超长指令字（VLIW）等）及其优化方法。 8. **动态调度和预测**：包括分支预测、调度算法，这些技术用于减少由于等待数据或指令引起的停滞。 9. **功耗管理**：在高性能处理器中，功耗是一个关键考虑因素，可能涵盖了动态电压频率调整（DVFS）、多电源域和低功耗设计策略。 10. **事务性内存（Transactional Memory）**：作为并发控制的一种新技术，书中可能对其原理、优缺点和实现方法进行了介绍。 11. **片上网络（On-Chip Networks）**：随着处理器集成度的提高，片上通信网络的重要性日益凸显，书中可能讨论了网络拓扑、协议和性能优化。 12. **可重构计算**：介绍如何通过改变硬件结构以适应不同的计算任务，例如FPGA（现场可编程门阵列）和GPU（图形处理器）的应用。 13. **性能评估模型**：书中可能包含了一些评估处理器性能的方法和工具，如SPEC基准测试，以及如何分析和预测处理器的性能。这本书是Synthesis Lectures on Computer Architecture系列的一部分，该系列专注于计算机体系结构的设计、分析和选择，旨在提供最新的科研和技术成果。通过阅读本书，读者将能够深入理解处理器微架构的实现细节，并掌握优化处理器性能的技巧。

6 PROCESSOR MICROARCHITECTURE: AN IMPLEMENTATION PERSPECTIVE

The ﬁrst part of the pipeline is responsible for fetching instructions. The main components of

this part of the pipeline are (a) an instruction cache, where instructions are stored, and (b) a branch

predictor that determines the address of the next fetch operation.

The next part is the instruction decode. The main components of this part are decoders,

ROMs and ad-hoc circuitry, whose main objective is to identify the main attributes of the instruc-

tion such as type (e.g., control ﬂow) and resources that it will require (e.g., register ports, functional

units).

Afterward, the instructions ﬂow to the allocation phase, where the two main actions that

are performed are register renaming and dispatch. Register renaming entails changing the names of

the register operands with the purpose of removing all false dependences and therefore maximiz-

ing the instruction-level parallelism that the processor can exploit. This is done normally through

a set of tables that contain information about the current mapping of logical names to physical

ones and what names are not being used at this point in time, together with some logic to analyze

dependences among the multiple instructions being renamed simultaneously, since the destination

and source register of a producer-consumer pair has to be renamed in a consistent manner. The

instruction dispatch consists of reserving different resources that the instruction will use, including

entries in the reorder buffer, issue queue and load/store buffers. If resources are not available, the

corresponding instruction is stalled until some other instruction releases the required resources.

The next phase in the pipeline is devoted to instruction issue. Instructions sit in the issue

queue until the issue logic determines that their execution can start. For in-order processors, the

issue logic is relatively simple. It basically consists of a scoreboard that indicates which operands are

available and a simple logic that checks whether the instructions sitting at the head of the queue

have all their operands ready. For out-of-order processors, this logic is quite complex since it entails

analyzing all the instructions in the queue at every cycle to check for readiness of their operands and

availability of the resources that they will require for execution.

After being issued, instructions go to the execution part of the pipeline. Here there is a variety

of execution units for different types of operations, which normally include integer, ﬂoating-point

and logical operations. It is also quite common nowadays to include special units for SIMD opera-

tions (single instruction, multiple data, also referred to as vector operations). Another important

component of the execution pipeline is the bypass logic. It consists basically of wires that can move

results from one unit to the input of other units and the associated logic that determines whether

results should use the bypass instead of using the data coming from the register ﬁle. The design of

the bypass network is critical in most processors since wire delays do not scale at the same pace as

gate delays, so they have an important contribution to the cycle time of the processor.

Finally, instructions move to the commit phase. The main purpose of this part of the pipeline

is to give the appearance of sequential execution (i.e., same outcome) even though instructions are

Caches store recently accessed program data and instructions, in the hope that they will be needed

in the near future, based on the observation that program memory accesses exhibit signiﬁcant spa-

tial and temporal locality. By buffering such frequently accessed data in a small and fast structure,

the processor can give the illusion to the application that accesses to main memory are in the order

of a few cycles.

Data caches usually are organized in hierarchies of between 1 and 3 levels, so we can talk

about the ﬁrst-level cache, the second-level cache, etc. The lower the level, the closer to the proces-

sor the cache is located. Level 1 data caches usually have low associativity and store several tens of

kilobytes of data arranged in cache blocks of around 64 bytes each, and they can be accessed in a few

cycles (between 1 and 4, usually). Normally, processors have two ﬁrst-level caches, one for program

data (the data cache) and one for program instructions (the instruction cache). Second- and third-

level caches are usually between several hundreds of kilobytes and a few megabytes in size, have very

high associativity and take tens of cycles to access. These caches usually hold both program data and

instructions. Moreover, although each core in a multicore processor has its own (private) ﬁrst-level

caches, higher levels of the memory hierarchy are usually shared among multiple cores. In this sec-

tion, we will focus the discussion on ﬁrst-level data caches.

Normally, program data and instruction addresses are virtual addresses. Load and store instruc-

tions as well as the fetch engine must perform address translation (more on this later) to translate

the virtual addresses to physical addresses. The caches can be indexed with either virtual or physical

addresses. In the former case, the cache access can be initiated earlier, since the address translation

can be performed in parallel with the cache access. To deal with potential aliasing problems, the tags

are normally generated from the physical address.

Load and store instructions have to take several steps in order to access the data cache. First,

the virtual address of the memory access has to be calculated in the address generation unit (AGU),

as will be discussed in Chapter 7. In the case of stores, the store queue is updated with this address,

and in the case of loads, the store queue is checked for disambiguation (Chapter 6). When the dis-

ambiguation logic decides that a load can proceed (or when a store reaches its commit phase), the

data cache is accessed.

C H A P T E R 2

Caches

10 PROCESSOR MICROARCHITECTURE: AN IMPLEMENTATION PERSPECTIVE

Instruction cache access is simpler, in that no disambiguation is required since stores to the

instruction cache are not allowed. The only requirement is to calculate the virtual address of the

instruction to be fetched. This process usually includes predicting the next instruction address, a

process that will be described in Chapter 3.

The rest of this chapter is organized as follows. First, we explain how virtual addresses are

translated to physical addresses. Then we discuss how caches are structured, and we describe several

alternatives for cache designs. We focus this discussion on the data cache because it has a more

complex pipeline compared to the instruction cache. Finally, we brieﬂy revisit the several alternative

cache designs, discussing the implications on the instruction cache.

2.1 ADDRESS TRANSLATION

The physical address space is deﬁned as the range of addresses that the processor can generate on its

bus. The virtual address space is the range of addresses that an application program can use. Virtual-

izing the program addresses serves two main purposes. First, it allows each program to run unmodi-

ﬁed on machines with different amounts of physical memory installed or on multitasking systems

where physical memory is shared among many applications. Second, by isolating the virtual address

spaces of different programs, we can protect applications from each other on multitasking systems.

The virtualization of the linear address space is handled through the processor’s paging mech-

anism. When using paging, the address space is divided into pages (typically 4–8 KB in size). A

page can reside either in the main memory or in the disk (a swapped-out page). The operating sys-

tem maintains a mapping of virtual pages to physical pages through a structure called the page table.

The page table usually is stored in the main memory.

It is possible for two virtual pages to map to the same physical page. This is typical, for ex-

ample, in shared-memory multithreaded applications. When this occurs, the two virtual pages are

“aliases” of the same physical entity, so this is called virtual aliasing. When implementing the data

cache, load/store buffers and all related management mechanisms, it is very important to be able to

handle virtual aliasing correctly.

When a program issues a load or store instruction, or an instruction fetch, the page map must

be consulted to translate the linear address to a physical address before the memory access can be

performed. A linear address is divided into two parts: the page offset and the page number. The page

offset corresponds to the N least signiﬁcant bits of the address—where N = log

(PAGE_SIZE)—and

identiﬁes a byte address inside a page. The page number—the remaining address bits—identiﬁes a

page inside the address space.

In a naive implementation, a load instruction (or instruction fetch) would have to perform

several memory accesses in order to translate the linear address to a physical one (the page table is in

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