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MT7682 Datasheet
© 2017 Airoha Technology Corp.
This document contains information that is proprietary to Airoha Technology Corp. (“Airoha”) and/or its licensor(s).
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• Embedded flash of 8Mbits to store programs and data.
96KB SRAMs are composed of TCMs and L1 caches. L1 cache (up to 32KB) is implemented to improve processor
access performance of the long latency memories (flash).
TCMs are designed for high speed, low latency and low power demanding applications. Each TCM has its own
power state; active, retention or power-down. TCM must be in active state for normal read and write access.
Retention state saves the SRAM content and consumes the minimum leakage current with no access. Power-down
loses the content and consumes almost zero power.
The TCMs can also be accessed by other internal AHB masters like DMA or multimedia sub-system for low power
applications. These applications can run on TCM without powering on flash to save more power.
Boot ROM is also implemented for processor boot-up and its content is unchangeable.
2.1.4. Memory protection unit (MPU)
The Memory Protection Unit (MPU) is an optional component to manage the CPU access to memory. The MPU
provides full support for:
• Protection regions (up to 8 regions and can be further divided up into 8 sub-regions).
• Overlapping protection regions, with region priority.
• Access permissions.
• Exporting memory attributes to the system.
The MPU is useful for applications where a critical code has to be protected against the misbehavior of other tasks.
It can be used to define access rules, enforce privilege rules and separate processes.
2.1.5. Nested vectored interrupt controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) supports up to 32 maskable interrupts and 16 interrupt lines of
Cortex-M4 with 32 priority levels. The NVIC and the processor core interface are closely coupled to enable low
latency interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of
the stacked or nested interrupts to enable tail-chaining of interrupts. The processor supports both level and pulse
interrupts with programmable active-high or low control.
2.1.6. External interrupt controller (EIC)
The external interrupt controller consists of up to 32 edge detectors for generating event/interrupt requests. Each
input line can be independently configured to select the type (interrupt or event) and the corresponding trigger
event (rising edge or falling edge or both or level). Each line can also be masked independently. A pending register
maintains the status line of the interrupt requests. Up to 21 GPIOs can be connected to 21 external interrupt lines.
2.1.7. Bus architecture
To better support various IoT applications, MT7682 adopts 32-bit multi-AHB matrix to provide low-power, fast and
flexible data operation. Table 2.1-1 shows the interconnections between bus masters and slaves.
The bus masters include Cortex-M4, SPM, SPI master, SPI slave, SDIO master, SDIO slave, Crypto engine, WIFI
(CONN) system and DMA.
The bus slaves include the Always On (AO) domain APB peripherals, Power Down (PD) domain APB peripherals,
TCM, SFC, EMI, SYSRAM, RTC SRAM, and WIFI (CONN) system.