MT7682：低功耗IoT Wi-Fi芯片技术规格

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"MT7682_Datasheet - MTK IOT Wifi芯片MT7682的技术规格说明书，强调其低功耗和快速唤醒功能。" MT7682是一款由Airoha Technology Corp.制造的物联网(IoT)Wi-Fi芯片，专门设计用于在物联网设备中提供高效、节能的无线连接。该芯片的数据手册，即MT7682 Datasheet，是Airoha公司的专有信息，其中包含了对芯片详细技术参数和功能的描述。使用者必须遵循与Airoha签订的相关许可协议才能访问和复制这份文档。根据 datasheet 的版本2.5，发布日期为2018年5月17日，我们可以推断这是该芯片的最新技术规格。MT7682的主要特性包括低功耗设计，这使得它在物联网设备中特别适合，因为这类设备通常需要长时间的电池寿命。此外，快速唤醒功能意味着设备可以迅速从休眠状态恢复到工作状态，这对于响应时间敏感的应用至关重要。该芯片支持Wi-Fi标准，可能包括802.11b/g/n，提供稳定的无线连接性能。数据手册可能会详细介绍其射频(RF)性能、传输速率、功耗模式、接口选项（如UART、SPI或I2C）、安全特性（如WPA/WPA2加密）以及硬件和软件开发工具。Airoha公司明确声明，他们不对文档内容或因使用该文档或无法使用而产生的任何问题承担任何责任，并且所有规格都可能在未通知的情况下变更。在实际应用中，开发者和制造商需要依据MT7682的datasheet来设计和优化他们的产品，确保与芯片的兼容性和性能。这可能涉及到天线设计、电源管理、固件开发以及与其它系统组件的集成。 datasheet 会提供必要的电气特性、尺寸信息、封装类型等，以帮助工程师进行硬件布局和PCB设计。 MT7682是一款适用于物联网的Wi-Fi芯片，其低功耗和快速唤醒特性使其成为智能设备和传感器网络的理想选择。开发者需要仔细阅读并理解MT7682 Datasheet，以便充分利用其优势并确保其在最终产品中的有效运行。

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MT7682 Datasheet

Page 11 of 62

This document contains information that is proprietary to Airoha Technology Corp. (“Airoha”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

• Embedded flash of 8Mbits to store programs and data.

96KB SRAMs are composed of TCMs and L1 caches. L1 cache (up to 32KB) is implemented to improve processor

access performance of the long latency memories (flash).

TCMs are designed for high speed, low latency and low power demanding applications. Each TCM has its own

power state; active, retention or power-down. TCM must be in active state for normal read and write access.

Retention state saves the SRAM content and consumes the minimum leakage current with no access. Power-down

loses the content and consumes almost zero power.

The TCMs can also be accessed by other internal AHB masters like DMA or multimedia sub-system for low power

applications. These applications can run on TCM without powering on flash to save more power.

Boot ROM is also implemented for processor boot-up and its content is unchangeable.

2.1.4. Memory protection unit (MPU)

The Memory Protection Unit (MPU) is an optional component to manage the CPU access to memory. The MPU

provides full support for:

• Protection regions (up to 8 regions and can be further divided up into 8 sub-regions).

• Overlapping protection regions, with region priority.

• Access permissions.

• Exporting memory attributes to the system.

The MPU is useful for applications where a critical code has to be protected against the misbehavior of other tasks.

It can be used to define access rules, enforce privilege rules and separate processes.

2.1.5. Nested vectored interrupt controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) supports up to 32 maskable interrupts and 16 interrupt lines of

Cortex-M4 with 32 priority levels. The NVIC and the processor core interface are closely coupled to enable low

latency interrupt processing and efficient processing of late arriving interrupts. The NVIC maintains knowledge of

the stacked or nested interrupts to enable tail-chaining of interrupts. The processor supports both level and pulse

interrupts with programmable active-high or low control.

2.1.6. External interrupt controller (EIC)

The external interrupt controller consists of up to 32 edge detectors for generating event/interrupt requests. Each

input line can be independently configured to select the type (interrupt or event) and the corresponding trigger

event (rising edge or falling edge or both or level). Each line can also be masked independently. A pending register

maintains the status line of the interrupt requests. Up to 21 GPIOs can be connected to 21 external interrupt lines.

2.1.7. Bus architecture

To better support various IoT applications, MT7682 adopts 32-bit multi-AHB matrix to provide low-power, fast and

flexible data operation. Table 2.1-1 shows the interconnections between bus masters and slaves.

The bus masters include Cortex-M4, SPM, SPI master, SPI slave, SDIO master, SDIO slave, Crypto engine, WIFI

(CONN) system and DMA.

The bus slaves include the Always On (AO) domain APB peripherals, Power Down (PD) domain APB peripherals,

TCM, SFC, EMI, SYSRAM, RTC SRAM, and WIFI (CONN) system.

MT7682 Datasheet

Page 13 of 62

This document contains information that is proprietary to Airoha Technology Corp. (“Airoha”) and/or its licensor(s).

Any unauthorized use, reproduction or disclosure of this document in whole or in part is strictly prohibited.

• Serial flash

• SPI slave (to load binary from host)

• SDIO slave (to load binary from host)

The host may transmit a binary through SPI slave or SDIO slave to internal system memory (SRAM). The MCU

(Cortex-M4) can execute on SRAM after transmission is complete. The boot source in boot ROM is determined

according to the flowchart shown in Figure 2.2-1. HIF_EN and HIF_SEL can be configured at power up using by

GPIO_4 and GPIO_13, respectively.

Boot from SDIO slave

HIF

_EN = 1?

HIF

_SEL = 1?

Boot from SPI slave Boot from Serial flash

Figure 2.2-1. Boot source determination flow

2.3. Clock architecture

The clock controller (see below Figure 2.3-1) distributes the clocks coming from different oscillators to the core

and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features:

• Clock prescaler. To get the best trade-off between speed and current consumption, the clock frequency to the

CPU and peripherals can be adjusted by a programmable prescaler.

• Safe clock switching. Clock sources can be changed safely at runtime through a configuration register.

• Clock management. To reduce the power consumption, the clock controller can stop the clock to the core,

individual peripherals or memory. The AHB and APB clock supports Dynamic Clock Management (DCM) with a

dynamic clock slow down or gating when the bus fabric is idle.

• System clock source. Two different clock sources can be used to drive the master clock (F

CPU

and F

BUS

o 26 MHz/40MHz Crystal Oscillator (XO), that can supply reference clock for PLLs.

o Baseband PLL1 (BBPLL1) which reference clock is XO, with a maximum frequency at 1040MHz.

o Baseband PLL2 (BBPLL2) which reference clock is XO or divided from BBPLL1, with a fixed frequency at

960MHz.

• Auxiliary clock source. Three ultra-low power clock sources that can be used to drive the real-time clock. In

32k-less mode, XO32K and EOSC32K are chosen, while in 32k mode only XOSC32K is used:

o 32.768 kHz low-speed external crystal (XOSC32K).

o 32.76 kHz or 32.745kHz low-speed internal clock divided from XO 40MHz or 26MHz (XO32K).

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