Core components
4.3.3 Writing to user information configuration registers (UICR)
User information configuration registers (UICR) are written in the same way as flash. After UICR has been
written, the new UICR configuration will take effect after a reset.
UICR can only be written n
WRITE
number of times before an erase must be performed using ERASEUICR on
page 21 or ERASEALL on page 21. The time it takes to write a word to UICR is specified by t
WRITE
.
The CPU is halted while the NVMC is writing to the UICR.
4.3.4 Erasing user information configuration registers (UICR)
When erase is enabled, UICR can be erased using the ERASEUICR on page 21.
After erasing UICR all bits in UICR are set to 1. The time it takes to erase UICR is specified by t
ERASEPAGE
. The
CPU is halted if the CPU executes code from the flash while the NVMC performs the erase operation.
4.3.5 Erase all
When erase is enabled, flash and UICR can be erased completely in one operation by using ERASEALL on
page 21. This operation will not erase the factory information configuration registers (FICR).
The time it takes to perform an ERASEALL command is specified by t
ERASEALL
. The CPU is halted if the CPU
executes code from the flash while the NVMC performs the erase operation.
4.3.6 Partial erase of a page in flash
Partial erase is a feature in the NVMC to split a page erase time into shorter chunks, so this can be used to
prevent longer CPU stalls in time-critical applications. Partial erase is only applicable to the code area in
the flash and does not work with UICR.
When erase is enabled, the partial erase of a flash page can be started by writing to ERASEPAGEPARTIAL
on page 22. The duration of a partial erase can be configured in ERASEPAGEPARTIALCFG on page
22. A flash page is erased when its erase time reaches t
ERASEPAGE
. Use ERASEPAGEPARTIAL N number
of times so that N * ERASEPAGEPARTIALCFG ≥ t
ERASEPAGE
, where N * ERASEPAGEPARTIALCFG gives the
cumulative (total) erase time. Every time the cumulative erase time reaches t
ERASEPAGE
, it counts as one
erase cycle.
After the erase is done, all bits in the page are set to '1'. The CPU is halted if the CPU executes code from
the flash while the NVMC performs the partial erase operation.
The bits in the page are undefined if the flash page erase is incomplete, i.e. if a partial erase has started
but the total erase time is less than t
ERASEPAGE
.
4.3.7 Registers
Base address Peripheral Instance Description Configuration
0x4001E000 NVMC NVMC Non-volatile memory controller
Table 5: Instances
Register Offset Description
READY 0x400 Ready flag
CONFIG 0x504 Configuration register
ERASEPAGE 0x508 Register for erasing a page in code area
ERASEPCR1 0x508 Register for erasing a page in code area. Equivalent to ERASEPAGE. Deprecated
ERASEALL 0x50C Register for erasing all non-volatile user memory
ERASEPCR0 0x510 Register for erasing a page in code area. Equivalent to ERASEPAGE. Deprecated
ERASEUICR 0x514 Register for erasing user information configuration registers
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