FXOS8700CQ：低功耗六轴传感器，集成加速度计与磁力计

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FXOS8700CQ是一款由Freescale Semiconductor提供的高性能、低功耗的六轴传感器，它集成了线性加速度计和磁强计功能。这款设备的独特之处在于其紧凑的单芯片设计，将三个关键传感器功能集成在一个小型塑料QFN封装内，旨在简化系统设计并优化空间利用。该传感器的核心特性包括： 1. **多量程选择**：FXOS8700CQ支持动态选择的数字I2C或点对点SPI串行接口，提供14位线性加速度计分辨率和16位磁强计分辨率。用户可以根据应用需求灵活调整加速度范围，可选择±2g、±4g或±8g的全量程，满足不同精度和灵敏度要求。 2. **固定磁感应范围**：磁强计部分具备固定的测量范围，为±1200微特斯拉（μT），这在定位和导航应用中十分实用。 3. **数据速率自定义**：用户可以设置输出数据速率（ODR），从低至1.563赫兹到高达800赫兹，甚至在400赫兹时提供磁性和加速度数据的交错输出，适应不同的实时处理和功耗需求。 4. **温度兼容性**：FXOS8700CQ经过优化，能在广泛的温度范围内稳定工作，确保在各种环境条件下都能提供准确的数据。 5. **能源效率**：作为一款节能解决方案，Freescale注重降低功耗，这对于电池驱动的移动设备尤为重要，有助于延长设备续航时间。 6. **文档支持**：该产品文档为Freescale Semiconductor的Data Sheet，技术规格版本为Rev.3.0，发布于2013年7月，包含了详细的产品功能描述、电气参数和使用指南，为开发人员提供了宝贵的参考资源。 FXOS8700CQ是工业设计和消费电子中不可或缺的组件，它的多功能性、灵活性和高效性使其成为现代智能设备中感知环境和进行运动跟踪的理想选择。设计者可以根据具体项目需求，调整传感器性能参数，确保系统的精确度、可靠性和整体性能。

FXOS8700CQ

Sensors

16 Freescale Semiconductor, Inc.

5.2 Magnetic characteristics (magnetometer)

5.3 Hybrid characteristics

Table 3. Magnetic characteristics @ VDD = 2.5 V, VDDIO = 1.8 V T = 25°C unless otherwise noted.

Parameter Test Conditions Symbol Min Typ Max Unit

Measurement range FS

MAG

±1200 μT

Sensitivity SEN

MAG

0.1 μT/LSB

Sensitivity change versus temperature TCS

MAG

±0.1 %/°C

Zero-flux offset accuracy

(1)

1. After m-cell has been factory trimmed

OFF

MAG

±10 μT

Zero-flux offset change with temperature TCO

MAG

±0.8 μT/°C

Hysteresis

(2)(3)

2. Hysteresis is measured by sweeping the applied magnetic field from -1000 μT to 1000 μT and then back to -1000 μT. The difference in the

two readings at -1000

μT divided by the swept field range is the hysteresis figure, expressed in % of the full-scale range (FS

MAG

HYST

MAG

±0.5 %FS

MAG

Nonlinearity

(3)

Deviation from best-fit straight line

3. Tested over a ±1000

μT measurement range.

MAG

±1 %FS

MAG

Temperature sensor sensitivity 0.96 °C/LSB

Magnetometer output noise

ODR = 800 Hz, OSR = 2

Noise

MAG

1.5

μT-rms

ODR = 400 Hz, OSR = 4 1.2

ODR = 200 Hz, OSR = 8 0.85

ODR = 100 Hz, OSR = 16 0.6

ODR = 50 Hz, OSR = 32 0.5

ODR = 12.5 Hz, OSR = 128 0.35

ODR = 6.25 Hz, OSR = 256 0.3

ODR = 1.56 Hz, OSR = 1024 0.3

Self-Test output change

(1)

X-axis

STOC

MAG

1161 LSB

Y-axis -1130 LSB

Z-axis -43 LSB

Operating temperature range Top -40 +85 °C

Table 4. Hybrid characteristics @ VDD = 2.5 V, VDDIO = 1.8 V T = 25°C unless otherwise noted.

Parameter Test Conditions Symbol Min Typ Max Unit

Maximum output data rate in hybrid mode ODR

max

400 Hz

Operating temperature range Top -40 +85 °C

Output-data bandwidth BW ODR/2 Hz

FXOS8700CQ

Sensors

20 Freescale Semiconductor, Inc.

6.1.1 General I

C operation

There are two signals associated with the I

C bus: the Serial Clock Line (SCL) and the Serial Data line (SDA). The latter is a

bidirectional line used for sending and receiving the data to/from the interface. External pullup resistors connected to VDDIO are

required for SDA and SCL. When the bus is free both the lines are high. The I

C interface is compliant with fast mode (400 kHz),

and normal mode (100 kHz) I

C standards. Operation at frequencies higher than 400 kHz is possible, but depends on several

factors including the pullup resistor values, and total bus capacitance (trace + device capacitance). See Table 10 for more

information.

A transaction on the bus is started through a start condition (ST) signal, which is defined as a HIGH-to-LOW transition on the

data line while the SCL line is held HIGH. After the ST signal has been transmitted by the master, the bus is considered busy.

The next byte of data transmitted contains the slave address in the first seven bits, and the eighth bit, the read/write bit, indicates

whether the master is receiving data from the slave or transmitting data to the slave. When an address is sent, each device in

the system compares the first seven bits after the ST condition with its own address. If they match, the device considers itself

addressed by the master. The 9th clock pulse, following the slave address byte (and each subsequent byte) is the acknowledge

(ACK). The transmitter must release the SDA line during the ACK period. The receiver must then pull the data line low so that it

remains stable low during the high period of the acknowledge clock period.

The number of bytes per transfer is unlimited. If a receiver can't receive another complete byte of data until it has performed some

other function, it can hold the clock line, SCL low to force the transmitter into a wait state. Data transfer only continues when the

receiver is ready for another byte and releases the data line. This delay action is called clock stretching. Not all receiver devices

support clock stretching. Not all master devices recognize clock stretching. This part does not use clock stretching.

A low to high transition on the SDA line while the SCL line is high is defined as a stop condition (SP) signal. A write or burst write

is always terminated by the master issuing the SP signal. A master should properly terminate a read by not acknowledging a byte

at the appropriate time in the protocol. A master may also issue a repeated start signal (SR) during a transfer

The slave addresses that may be assigned to the FXOS8700CQ part are 0x1C, 0x1D, 0x1E, or 0x1F. The selection is made

through the logic level of the SA1 and SA0 inputs.

6.1.2 I

C Read/Write operations

Single-byte read

The master (or MCU) transmits a start condition (ST) to the FXOS8700CQ, followed by the slave address, with the R/W bit set

to “0” for a write, and the FXOS8700CQ sends an acknowledgement. Then the master (or MCU) transmits the address of the

(SR), followed by the slave address with the R/W bit set to “1” for a read from the previously selected register. The FXOS8700CQ

then acknowledges and transmits the data from the requested register. The master does not acknowledge (NAK) the transmitted

data, but transmits a stop condition to end the data transfer.

Multiple-byte read

When performing a multi-byte or “burst” read, the FXOS8700CQ automatically increments the register address read pointer after

a read command is received. Therefore, after following the steps of a single-byte read, multiple bytes of data can be read from

sequential registers after each FXOS8700CQ acknowledgment (AK) is received until a no acknowledge (NAK) occurs from the

master followed by a stop condition (SP) signaling an end of transmission.

Single-byte write

To start a write command, the master transmits a start condition (ST) to the FXOS8700CQ, followed by the slave address with the

R/W bit set to “0” for a write, and the FXOS8700CQ sends an acknowledgement. Then the master (or MCU) transmits the address

of the register to write to, and the FXOS8700CQ sends an acknowledgement. Then the master (or MCU) transmits the 8-bit data

to write to the designated register and the FXOS8700CQ sends an acknowledgement that it has received the data. Since this

transmission is complete, the master transmits a stop condition (SP) to end the data transfer. The data sent to the FXOS8700CQ

is now stored in the appropriate register.

Table 10. I

C slave address

SA1 SA0 Slave address

0 0 0x1E

010x1D

100x1C

1 1 0x1F

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