Designing with EZ-USB FX2LP™ Slave FIFO Interface using FPGA
www.cypress.com Document No. 001-61345 Rev. *H 3
FPGA Code Architecture
The main function of the FPGA code is to monitor the Full
and Empty flags of the Slave FIFO, and then read and
write into the FIFOs accordingly.
Both Verilog and VHDL projects are implemented to show
how to configure an FPGA to act as a master to an FX2LP
Slave-FIFO. Xilinx ISE Design Suite is used for code
development.
Data Loopback
Any data written into the EP2 FIFO of FX2LP is read by
the FPGA, and written into the EP6 FIFO. The associated
project folder, Loopback (attached with this application
note) contains this project.
Figure 3. Loop Back State Diagram
loop_back_idle
slrd = 1
sloe = 1
slwr = 1
faddr = 00
loop_back_read
slrd = 0
sloe = 0
slwr = 1
faddr = 00
loop_back_wait_
flagd
slrd = 1
sloe = 1
slwr = 1
faddr = 10
loop_back_write
slrd = 1
sloe = 1
slwr = 0
faddr = 10
flaga == 1
Flaga == 0
Flagd == 1
Flagd == 0 or fifo_empty == 1
slrd = 1, sloe = 1
slwr = 1
State loop_back_idle is the idle state in which the SLRD,
SLOE, and SLWR signals are high (de-asserted).The
state machine moves to loop_back_read state when EP2
FIFO Empty flag (Flag A) becomes High. In
loop_back_read, FPGA reads data by asserting both
SLRD and SLOE. State machine moves to
loop_back_wait_flagd state when EP2 FIFO Empty flag
becomes Low. During this transition SLRD and SLOE
signals are de-asserted. In loop_back_wait_flagd state,
FIFO address lines are driven to address EP6. It stays in
this state till EP6 Full flag (Flag D) is Low. State machine
moves to loop_back_write state when Flag D becomes
high. In this state, FPGA writes same data to EP6 FIFO by
asserting SLWR signal.
Stream IN Transfers
The FPGA monitors the Full flag of EP6 (Flag D) and Sync
signal. FPGA continuously writes incrementing data into
the FIFO when both Flag D and Sync signals are high.
While writing data into the EP6 FIFO, the FPGA pauses
the writing as soon as the Full flag gets asserted, and
resumes the writing when the flag gets de-asserted. The
associated project folder, Stream IN contains this project.
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