博通BCM5396：单芯片16端口SerDes千兆交换解决方案

网络交换芯片手册

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"博通BCM5396是一款单芯片16端口SerDes千兆交换芯片，专为桌面交换解决方案或WebSmart应用提供最低成本的千兆以太网功能。该芯片高度集成，包含高速交换系统的所有功能，如包缓冲器、媒体访问控制器（MACs）、地址管理以及无阻塞交换控制器，并符合IEEE 802.3系列标准，确保与所有行业标准以太网、快速以太网和千兆以太网设备兼容。" 博通BCM5396网络交换芯片是一款高效能的网络解决方案，它在一个0.13微米的CMOS单片芯片上集成了16个1.25G SerDes/SGMII端口接口。这些接口可以连接到外部的千兆物理层（PHY）或光纤模块，极大地减少了主板的空间占用。SerDes（串行化/解串行化）技术使得数据传输更高效，降低了系统的复杂性和成本。 BCM5396的主要特点包括： 1. **16个千兆端口**：提供16个独立的10/100/1000Mbps以太网端口，每个端口都支持SerDes或SGMII接口，能够灵活地适应不同的网络环境。 2. **高度集成**：该芯片将包缓冲、MACs、地址管理和无阻塞交换控制器等功能集成在一起，减少了对外部组件的需求，简化了系统设计。 3. **兼容性**：符合IEEE 802.3系列标准，包括802.3u（快速以太网）、802.3ab（千兆以太网铜线）和802.3x（流量控制）规范，确保与各种标准以太网设备无缝对接。 4. **MAC控制PAUSE帧**：支持MAC控制PAUSE帧功能，允许在网络出现拥塞时进行流量控制，保持网络的稳定性。 5. **自动协商**：支持自动协商子部分，可以自动检测并适应连接设备的速度和双工模式，简化配置过程。 6. **无阻塞交换**：采用无阻塞交换控制器设计，确保在所有端口全速运行时，数据传输不出现瓶颈，提供高带宽和低延迟的性能。 7. **地址管理**：内置的地址管理功能有助于维护网络中的设备连接和通信，实现有效的路由和过滤。博通BCM5396适用于桌面级交换机和WebSmart应用，这种类型的芯片通常用于企业网络、数据中心或智能网络设备中，提供高性能、低成本的网络连接方案。其紧凑的封装和强大的功能使其成为构建高效网络基础设施的理想选择。

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List of Figures BCM5396 Data Sheet

BROADCOM Single-Chip 16-Port SerDes Gigabit Switch

October 4, 2013 • 5396-DS114-R Page 16

BROADCOM CONFIDENTIAL

List of Figures

Figure 1: Functional Block Diagram....................................................................................................................2

Figure 2: Priority Packet Mapping Flow ...........................................................................................................27

Figure 3: VLAN Table Organization...................................................................................................................31

Figure 4: Bucket Flow .......................................................................................................................................34

Figure 5: Mirror Filter Flow ..............................................................................................................................36

Figure 6: Address Table Organization...............................................................................................................39

Figure 7: TXQ and Buffer Tag Structure............................................................................................................54

Figure 8: RvMII Port Connections.....................................................................................................................57

Figure 9: Normal SPI Command Byte ...............................................................................................................61

Figure 10: Fast SPI Command Byte...................................................................................................................61

Figure 11: SPI Serial Interface Write Operation ...............................................................................................62

Figure 12: SPI Serial Interface Read Operation ................................................................................................62

Figure 13: Normal SPI Mode Read Flow Chart .................................................................................................63

Figure 14: Normal SPI Mode Write Flow Chart ................................................................................................65

Figure 15: Timing Example ...............................................................................................................................66

Figure 16: Serial EEPROM Connection .............................................................................................................67

Figure 17: MDC/MDIO Interface ......................................................................................................................68

Figure 18: Read Access to Switch via Pseudo-PHY (PHY ADD = 1_1110) MDC[0]/MDIO[0] Path.....................69

Figure 19: Write Access to Switch via Pseudo-PHY (PHY ADD = 1_1110) MDC[0]/MDIO[0] Path....................70

Figure 20: Pseudo-PHY MII Register Map.........................................................................................................71

Figure 21: Pins Top View ..................................................................................................................................88

Figure 22: Reset and Clock Timing .................................................................................................................182

Figure 23: RvMII Mode Output Timings .........................................................................................................183

Figure 24: RvMII Mode Input Timings ............................................................................................................183

Figure 25: RGMII Output Timing (Normal Mode)...........................................................................................184

Figure 26: RGMII Output Timing (Delayed Mode)..........................................................................................185

Figure 27: RGMII Input Timing (Normal Mode)..............................................................................................186

Figure 28: RGMII Input Timing (Delayed Mode).............................................................................................187

Figure 29: GMII Output Timing.......................................................................................................................188

Figure 30: GMII Input Timing..........................................................................................................................188

Figure 31: Serial Interface Output Timing ......................................................................................................189

Figure 32: Serial Interface Input Timing .........................................................................................................190

Figure 33: MDC/MDIO Timing ........................................................................................................................190

Figure 34: Serial LED Interface Timing............................................................................................................191

Figure 35: SPI Timings, SS

Asserted During SCK High .....................................................................................192

List of Tables BCM5396 Data Sheet

BROADCOM Single-Chip 16-Port SerDes Gigabit Switch

October 4, 2013 • 5396-DS114-R Page 18

BROADCOM CONFIDENTIAL

List of Tables

Table 1: Frame Priority Decision Tree Summary ..............................................................................................30

Table 2: Bucket Bit Rate ...................................................................................................................................35

Table 3: Unicast Forward Field Definitions.......................................................................................................41

Table 4: Address Table Entry for Unicast Address............................................................................................41

Table 5: Multicast Forward Field Definitions ...................................................................................................43

Table 6: Address Table Entry for Multicast ARL Address..................................................................................43

Table 7: Behavior for Reserved Multicast Addresses.......................................................................................44

Table 8: Spanning Tree State............................................................................................................................49

Table 9: SGMII and SerDes Auto-Negotiation ..................................................................................................56

Table 10: Transmit/Receive Frame Format Over Management Port ...............................................................58

Table 11: OPCODE Field in BRCM Tag for Management Port Frame ...............................................................58

Table 12: IMP Broadcom TAG RX from CPU .....................................................................................................59

Table 13: IMP Broadcom TAG TX to CPU..........................................................................................................60

Table 14: EEPROM_EXT[1:0] Settings...............................................................................................................66

Table 15: EEPROM Header Format...................................................................................................................67

Table 16: EEPROM Contents ............................................................................................................................67

Table 17: Pseudo-PHY MII Register Definitions................................................................................................72

Table 18: MII Management Frame Format ......................................................................................................73

Table 19: Serial LED Mode Matrix ....................................................................................................................74

Table 20: Serial LED Status Types .....................................................................................................................75

Table 21: Load Meter LED Decode ...................................................................................................................75

Table 22: I/O Signal Type Definitions ...............................................................................................................77

Table 23: Signal Descriptions............................................................................................................................78

Table 24: Pin Assignment (Listed by Pin Number) ...........................................................................................84

Table 25: Pin Assignment (Listed by Signal Name)...........................................................................................86

Table 26: Global Page Register Map.................................................................................................................89

Table 27: Control Registers (Page 00h) ............................................................................................................92

Table 28: 10/100/1000 Port Control Register (Page 00h: Address 00h–0Fh) ..................................................94

Table 29: IMP Port Control Register (Page 00h: Address 10h).........................................................................94

Table 30: Switch Mode Register (Page 00h: Address 20h)...............................................................................95

Table 31: LED A Register (Page 00h: Address 24h–25h)...................................................................................96

Table 32: New Control Register (Page 00h: Address 3Bh) ...............................................................................96

Table 33: Reserved Multicast Register (Page 00h: Address 50h) .....................................................................97

Table 34: Load Meter Update Rate Control Register (Page 00h: Address 51h) ...............................................97

Table 35: Unicast Lookup Failed Forward Map Register (Page 00h: 54h–57h)................................................98

List of Tables BCM5396 Data Sheet

BROADCOM Single-Chip 16-Port SerDes Gigabit Switch

October 4, 2013 • 5396-DS114-R Page 19

BROADCOM CONFIDENTIAL

Table 36: Multicast Lookup Failed Forward Map Register (Page 00h: Address 58h–5Bh)...............................98

Table 37: Port N State Override Register (Page 00h: Address 60–6Fh)............................................................98

Table 38: Port 16 (IMP) State Override Register (Page 00h: Address 70h) ......................................................99

Table 39: 802.1X Control Register 1 (Page 00h: Address 77h) .......................................................................100

Table 40: 802.1X Control Register 2 (Page 00h: Address 78h–7Bh)...............................................................100

Table 41: SerDes Default Values Register (Page 00h: Address 80h–83h) ......................................................100

Table 42: SerDes Select Early Version of CRS and COL Register (Page 00h: Address 84h–85h).....................101

Table 43: External PHY Scan Control Register (Page 00h: Address 86h) ........................................................101

Table 44: Fast Aging Control Register (Page 00h: Address 88h) ....................................................................102

Table 45: Fast Aging Port Register (Page 00h: Address 89h)..........................................................................102

Table 46: Fast Aging VID Register (Page 00h: Address 138d–139d, 8Ah–8Bh) ..............................................102

Table 47: Pause Frame Detection Control Register (Page 00h: Address 90h)................................................103

Table 48: Status Registers (Page 01h) ............................................................................................................104

Table 49: Link Status Summary Register (Page 01h: Address 00h–03h) ........................................................105

Table 50: Link Status Change Register (Page 01h: Address 04h–07h)............................................................105

Table 51: Port Speed Summary Register (Page 01h: Address 08h–0Fh) ........................................................105

Table 52: Duplex Status Summary Register (Page 01h: Address 10h–13h) ...................................................106

Table 53: TX PAUSE Status Summary Register (Page 01h: Address 14h–17h) ...............................................106

Table 54: RX PAUSE Status Summary Register (Page 01h: Address 18h–1Bh)...............................................106

Table 55: Port N PHY Status Register (Page 01h: Address 20–2Fh)................................................................107

Table 56: SerDes Signal Detect Status Register (Page 01h: Address 40h)......................................................107

Table 57: BIST Status Register (Page 01h, Address 46h) ................................................................................107

Table 58: Strap Value Register (Page 01h: Address 70h–73h) .......................................................................108

Table 59: Management Mode Registers (Page 02h) ......................................................................................109

Table 60: Global Management Configuration Register (Page 02h: Address 00h) ..........................................109

Table 61: Aging Time Control Register (Page 02h: Address 0Ch–0Fh) ...........................................................110

Table 62: Mirror Capture Control Register (Page 02h: Address 10h–11h).....................................................110

Table 63: Ingress Mirror Control Register (Page 02h: Address 12h–15h) ......................................................111

Table 64: Ingress Mirror Divider Register (Page 02h: Address 16h–17h).......................................................111

Table 65: Egress Mirror Control Register (Page 02h: Address 1Ch–1Fh) .......................................................112

Table 66: Model ID Register (Page 02h: Address 30h) ...................................................................................112

Table 67: Revision ID Register (Page 02h: Address 40h) ................................................................................112

Table 68: ARL Control Registers (Page 04h) ...................................................................................................113

Table 69: Global ARL Configuration Register (Page 04h: Address 00h)..........................................................113

Table 70: BPDU Multicast Address Register (Page 04h: Address 04h–09h)...................................................114

Table 71: Multiport Address 1 Register (Page 04h: Address 10h–15h)..........................................................114

List of Tables BCM5396 Data Sheet

BROADCOM Single-Chip 16-Port SerDes Gigabit Switch

October 4, 2013 • 5396-DS114-R Page 20

BROADCOM CONFIDENTIAL

Table 72: Multiport Vector 1 Register (Page 04h: Address 16h–19h)............................................................114

Table 73: Multiport Address 2 Register (Page 04h: Address 20h–25h)..........................................................115

Table 74: Multiport Vector 2 Register (Page 04h: Address 26h–29h)............................................................115

Table 75: ARL/VLAN Access Registers (Page 05h) ..........................................................................................115

Table 76: ARL Read/Write Control Register (Page 05h: Address 00h) ...........................................................116

Table 77: MAC Address Index Register (Page 05h: Address 02h–07h) ..........................................................117

Table 78: VID Index Register (Page 05h: Address 08h–09h) ..........................................................................117

Table 79: ARL MAC/VID Entry 0 Register (Page 05h: Address 10h–17h) .......................................................117

Table 80: ARL FWD Entry 0 Register (Page 05h: Address 18h–1Bh)...............................................................118

Table 81: ARL MAC/VID Entry 1 Register (Page 05h: Address 20h–27h) .......................................................119

Table 82: ARL FWD Entry 1 Register (Page 05h: Address 28h–2Bh)...............................................................119

Table 83: ARL Search Control Register (Page 05h: Address 30h) ...................................................................120

Table 84: ARL Search Address Register (Page 05h: Address 31h–32h) ..........................................................121

Table 85: ARL Search MAC/VID Result Register 0 (Page 05h: Address 33h–3Ah) ..........................................121

Table 86: ARL Search Result Register 0 (Page 05h: Address 3Bh–3Eh) ..........................................................121

Table 87: ARL Search MAC/VID Result Register 1 (Page 05h: Address 40h–47h) ..........................................122

Table 88: ARL Search Result Register 1 (Page 05h: Address 48h–4Bh) ..........................................................122

Table 89: VLAN Table Read/Write Control Register (Page 05h: Address 60h)...............................................124

Table 90: VLAN Table Address Index Register (Page 05h: Address 61h–62h)................................................124

Table 91: VLAN Table Entry Register (Page 05h: Address 63h–6Ah)..............................................................124

Table 92: Flow Control Registers (Page 0Ah) .................................................................................................125

Table 93: Internal SerDes Registers Page Descriptions 10h–1Fh ...................................................................129

Table 94: Internal SerDes Registers Page 10h–1Fh ........................................................................................129

Table 95: MII Control (Page 10h–1Fh: Address 00h–01h)..............................................................................131

Table 96: MII Status (Page 10h–1Fh: Address 02h–03h)................................................................................132

Table 97: Auto-Negotiation Advertisement (Page 10h–1Fh: Address 08h–09h) ...........................................133

Table 98: Auto-Negotiation Link Partner Ability (Page 10h–1Fh: Address 0Ah–0Bh) ....................................134

Table 99: Auto-Negotiation Expansion (Page 10h–1Fh: Address 0Ch–0Dh) ..................................................135

Table 100: Extended Status (Page 10h–1Fh: Address 1Eh–1Fh) ....................................................................135

Table 101: SerDes/SGMII Control1 (Page 10h–1Fh: Address 20h–21h, Block 0) ...........................................136

Table 102: Analog Transmit Register (Page 10h ~ 1Fh: Address 20h ~ 21h, Block 1).....................................138

Table 103: SerDes/SGMII Control 2 (Page 10h–1Fh: Address 22h–23h)........................................................138

Table 104: SerDes/SGMII Control 3 (Page 10h–1Fh: Address 24h–25h)........................................................139

Table 105: SerDes/SGMII Status 1 (Page 10h–1Fh: Address 28h–29h)..........................................................140

Table 106: SerDes/SGMII Status 2 (Page 10h–1Fh: Address 2Ah–2Bh) .........................................................141

Table 107: SerDes/SGMII Status 3 (Page 10h–1Fh: Address 2Ch–2Dh) .........................................................142

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