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User’s Manual
Preliminary PowerPC 476FP Embedded Processor Core
Version 1.5
April 13, 2011
Revision Log
Page 19 of 318
Revision Log
Revision Date Description
April 13, 2011 Version 1.5
• Added “PowerPC 470S Synthesizable Core” to the title page and a reference to the 407S core in About
this Document on page 21.
•Revised Section 4.2 Address Translation on page 99.
•Revised Figure 4-1 Address Mapping for each Page Size on page 100.
•Revised Table 4-3 UTLB Tag Field Description on page 104.
•Revised Table 4-5 UTLB Data Field Description on page 106.
•Revised Table A-1 Register Categories on page 259.
January 19, 2011 Version 1.4
• Changed SSPCR to ISPCR in Section 4.3.12 Invalidating UTLB Entries on page 109.
• Made the following changes in Section 4.8.4 TLB Invalidate, Virtual Address Indexed (tlbivax) on
page 126:
– Removed a reference to tlbivax.
– Changed SSPCR to ISPCR.
– Removed a reference to USPCR entries.
– Changed isync to tlbsync.
• Added references to SPR addresses of x‘23C’ and x‘33C’ in Section 7.4.12 Machine Check Syndrome
Register (MCSR) on page 177.
November 23, 2010 Version 1.3
• Removed a reference to the mfapidi instruction in Section 2.3.1 Defined Instruction Class on page 45.
• Changed SPRG7 to SPRG8 in Section 2.7.1 Special Purpose Registers General (USPRG0, SPRG0 -
SPRG8) on page 65.
• Added bit 21 DPC to Core Configuration Register 1 (CCR1) on page 68.
• Made corrections to text and code in Section 4.8.2 TLB Read Entry (tlbre) on page 124 and Section 4.8.3
TLB Write Entry (tlbwe) on page 125.
• Added information that tlbivax and tlbsync are never executed simultaneously in Section 4.9 UTLB
Coherency on page 126.
• Added information that an isync must follow an ici instruction in Section 5.2.2.3 Instruction Cache Invali-
date (ici) on page 131.
• Added information that an isync instead of an msync can follow a dci instruction in Section 5.5.12 Data
Cache Invalidate (dci) on page 142.
• Changed “privileged instructions cannot be executed” to read “the processor is in privileged state” for bit
49 in Section 7.4.1 Machine State Register (MSR) on page 169.
• Removed a reference to tlbiva in Section 7.5.7 Program Interrupt on page 189.
• Changed dccci to dci, iccci to ici, and removed a reference to tlbiva in Section 7.7.6 Exception Priori-
ties for Privileged Instructions on page 210.
• Added Section 8.6 JTAG and Debug Capabilities in a Multiprocessor SoC Environment on page 237.
• Added substeps to step 4 in Section 9.4 Initialization Software Requirements on page 246.
• Made minor updates to Table 10-3 Cache Operations on page 255.
• Made minor updates to Section A Register Summary on page 259.
• Moved the Debug Bus Out Mask Register (DBOMask) from Appendix A to Section 8.6.1 Debug Bus Out
Mask Register (DBOMask) on page 237.
• Moved the Debug Input Mask Register (DBIMask) from Appendix A to Section 8.6.2 Debug Input Mask
Register (DBIMask) on page 238.
September 16, 2010 Version 1.2
Made minor technical corrections to the following sections:
• Section 1 Overview on page 23
• Section 4.3.3 Initialize a Single UTLB Entry on page 103
• Section 4.6.9 Reset Configuration Register (RSTCFG) on page 122
• Section 4.8.3 TLB Write Entry (tlbwe) on page 125
• Section 5.1 Cache Array Organization and Operation on page 129
• Section 9.4 Initialization Software Requirements (step f on page 248)