PowerPC 476FP嵌入式处理器核心用户指南

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User’s Manual

PowerPC 476FP Embedded Processor Core Preliminary

List of Tables

Page 16 of 318

Version 1.5

April 13, 2011

Table 3-7. Floating-Point Move Instructions ............................................................................................96

Table 3-8. Floating-Point Elementary Arithmetic Instructions ..................................................................96

Table 3-9. Floating-Point Multiply-Add Instructions .................................................................................97

Table 3-10. Floating-Point Rounding and Conversion Instructions ...........................................................97

Table 3-11. Comparison Sets ....................................................................................................................98

Table 3-12. Floating-Point Compare and Select Instructions ....................................................................98

Table 3-13. Floating-Point Status and Control Register Instructions .........................................................98

Table 4-1. PowerPC 476FP Processor MMU ..........................................................................................99

Table 4-2. UTLB Set Address Generation Hashing Function ................................................................103

Table 4-3. UTLB Tag Field Description .................................................................................................104

Table 4-4. EPN and EA Comparison .....................................................................................................105

Table 4-5. UTLB Data Field Description ................................................................................................106

Table 4-6. Access Control Applied to Cache Management Instructions ................................................113

Table 4-7. MMU SPR Summary ............................................................................................................115

Table 5-1. Instruction and Data Cache Array Organization ...................................................................129

Table 5-2. Cache Size and Parameters .................................................................................................130

Table 5-3. EA Format icread .................................................................................................................132

Table 5-4. ICU Special Purpose Registers ............................................................................................135

Table 5-5. Effective Address Format for icread and dcread .................................................................147

Table 6-1. Timer Register Summary ......................................................................................................154

Table 6-2. Fixed-Interval Timer Period Selection ..................................................................................157

Table 6-3. Watchdog Timer Period Selection ........................................................................................157

Table 6-4. Watchdog Timer Exception Behavior ...................................................................................158

Table 7-1. Interrupt Types Associated with each IVOR .........................................................................174

Table 7-2. Interrupt and Exception Types ..............................................................................................179

Table 7-3. BRT Debug Event Actions ....................................................................................................198

Table 7-4. TRAP Debug Event Actions .................................................................................................199

Table 7-5. RET Debug Event Actions ....................................................................................................199

Table 7-6. ICMP Debug Event Actions ..................................................................................................200

Table 7-7. IRPT Debug Event Actions ...................................................................................................200

Table 7-8. UDE Debug Event Actions ...................................................................................................200

Table 8-1. IAC Range Mode Toggle Summary ......................................................................................219

Table 8-2. Trap Debug Event Actions ....................................................................................................226

Table 8-3. BRT Debug Event Actions ....................................................................................................227

Table 8-4. ICMP Debug Event Actions ..................................................................................................227

Table 8-5. RET Debug Event Actions ....................................................................................................228

Table 8-6. IRPT Debug Event Actions ...................................................................................................229

Table 8-7. UDE Debug Event Actions ...................................................................................................230

Table 8-8. Setting the DBSR based on MSR[DE] and DBCR0[IDM] .....................................................236

User’s Manual

Preliminary PowerPC 476FP Embedded Processor Core

Version 1.5

April 13, 2011

Revision Log

Page 19 of 318

Revision Log

Revision Date Description

April 13, 2011 Version 1.5

• Added “PowerPC 470S Synthesizable Core” to the title page and a reference to the 407S core in About

this Document on page 21.

•Revised Section 4.2 Address Translation on page 99.

•Revised Figure 4-1 Address Mapping for each Page Size on page 100.

•Revised Table 4-3 UTLB Tag Field Description on page 104.

•Revised Table 4-5 UTLB Data Field Description on page 106.

•Revised Table A-1 Register Categories on page 259.

January 19, 2011 Version 1.4

• Changed SSPCR to ISPCR in Section 4.3.12 Invalidating UTLB Entries on page 109.

• Made the following changes in Section 4.8.4 TLB Invalidate, Virtual Address Indexed (tlbivax) on

page 126:

– Removed a reference to tlbivax.

– Changed SSPCR to ISPCR.

– Removed a reference to USPCR entries.

– Changed isync to tlbsync.

• Added references to SPR addresses of x‘23C’ and x‘33C’ in Section 7.4.12 Machine Check Syndrome

November 23, 2010 Version 1.3

• Removed a reference to the mfapidi instruction in Section 2.3.1 Defined Instruction Class on page 45.

• Changed SPRG7 to SPRG8 in Section 2.7.1 Special Purpose Registers General (USPRG0, SPRG0 -

SPRG8) on page 65.

• Added bit 21 DPC to Core Configuration Register 1 (CCR1) on page 68.

• Made corrections to text and code in Section 4.8.2 TLB Read Entry (tlbre) on page 124 and Section 4.8.3

TLB Write Entry (tlbwe) on page 125.

• Added information that tlbivax and tlbsync are never executed simultaneously in Section 4.9 UTLB

Coherency on page 126.

• Added information that an isync must follow an ici instruction in Section 5.2.2.3 Instruction Cache Invali-

date (ici) on page 131.

• Added information that an isync instead of an msync can follow a dci instruction in Section 5.5.12 Data

Cache Invalidate (dci) on page 142.

• Changed “privileged instructions cannot be executed” to read “the processor is in privileged state” for bit

49 in Section 7.4.1 Machine State Register (MSR) on page 169.

• Removed a reference to tlbiva in Section 7.5.7 Program Interrupt on page 189.

• Changed dccci to dci, iccci to ici, and removed a reference to tlbiva in Section 7.7.6 Exception Priori-

ties for Privileged Instructions on page 210.

• Added Section 8.6 JTAG and Debug Capabilities in a Multiprocessor SoC Environment on page 237.

• Added substeps to step 4 in Section 9.4 Initialization Software Requirements on page 246.

• Made minor updates to Table 10-3 Cache Operations on page 255.

• Made minor updates to Section A Register Summary on page 259.

• Moved the Debug Bus Out Mask Register (DBOMask) from Appendix A to Section 8.6.1 Debug Bus Out

Mask Register (DBOMask) on page 237.

• Moved the Debug Input Mask Register (DBIMask) from Appendix A to Section 8.6.2 Debug Input Mask

September 16, 2010 Version 1.2

Made minor technical corrections to the following sections:

• Section 1 Overview on page 23

• Section 4.3.3 Initialize a Single UTLB Entry on page 103

• Section 4.6.9 Reset Configuration Register (RSTCFG) on page 122

• Section 4.8.3 TLB Write Entry (tlbwe) on page 125

• Section 5.1 Cache Array Organization and Operation on page 129

• Section 9.4 Initialization Software Requirements (step f on page 248)

User’s Manual

PowerPC 476FP Embedded Processor Core Preliminary

Revision Log

Page 20 of 318

Version 1.5

April 13, 2011

September 1, 2010 Version 1.1

• Made various changes to the following sections:

– Section 1.2 Power Control Features on page 24

– Section 2.2 Registers on page 38

– Section 2.11 Storage Model on page 78

– Section 3.2 Floating-Point Registers on page 82

– Section 3.4 Floating-Point Instructions on page 91

– Section 4.3 MMU Implementation on page 100

– Section 4.4 Access Control on page 109

– Section 4.10 tlbsync Special Operations on page 127

– Section 5 Instruction and Data Caches on page 129

– Section 5.1 Cache Array Organization and Operation on page 129

– Section 5.2 Instruction Cache Controller on page 130

– Section 5.3 ICU Special Purpose Registers on page 135

– Section 5.4 Self-Modifying Code on page 136

– Section 5.5 Data Cache Controller on page 137

– Section 7.1 Overview on page 163

– Section 7.5 Interrupt Definitions on page 178

– Section 8 Debug Facilities on page 213 (throughout the entire chapter)

– Section 10.2 L2 Cache Features on page 253

– Section 10.3 L1 Cache UTLB Snoop Interface on page 257

– Appendix A Register Summary on page 259

• Changed the register bit numbers from [0:31] to [32:63] in the following sections:

– Section 2.5.5.2 Count Register (CTR) on page 58

– Section 2.5.5.3 Condition Register (CR) on page 58

– Section 2.6.1 General Purpose Registers (GPRs) on page 61

– Section 2.6.2 Fixed-Point Exception Register (XER) on page 62

– Section 2.7.1 Special Purpose Registers General (USPRG0, SPRG0 - SPRG8) on page 65

– Section 2.7.2 Processor Version Register (PVR) on page 66

– Section 2.7.3 Processor Identification Register (PIR) on page 66

– Section 3.2.1.2 Floating-Point Status and Control Register (FPSCR) on page 83

– Section 6.5 Timer Control Register on page 159

– Section 6.6 Timer Status Register on page 160

– Section 7.4.1 Machine State Register (MSR) on page 169

– Section 7.4.2 Save/Restore Register 0 (SRR0) on page 170

– Section 7.4.4 Critical Save/Restore Register 0 (CSRR0) on page 171

– Section 7.4.5 Critical Save/Restore Register 1 (CSRR1) on page 172

– Section 7.4.6 Machine Check Save/Restore Register 0 (MCSRR0) on page 172

– Appendix A Register Summary on page 259

• Added new Appendix C Instruction Execution Performance for Code Optimization on page 275

September 15, 2009 Initial release.

Revision Date Description

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