南亚 DDR3 SDRAM NTC-DDR3-1Gb-G-V14 技术规格与应用

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"南亚DDR3 SDRAM NTC-DDR3-1Gb-G-V14是一种内存芯片，适用于商业、工业和汽车应用领域。这款内存符合JEDEC DDR3标准，具备8n预取架构，使用差分时钟(CK/CK#)和数据 strobe (DQS/DQS#)，并实现数据线上的双速率传输。它还提供了多种数据完整性保障机制，如内置温度传感器的自动自刷新(ASR)、自动刷新和自刷新模式。此外，该芯片支持节能模式，如部分数组自刷新(PASR)和电源下降模式，并有不同CAS延迟选项，包括6、7、8、9、10、11、12、13和14。" 南亚DDR3 SDRAM NTC-DDR3-1Gb-G-V14是南亚科技公司生产的一款1GB容量的DDR3 SDRAM内存颗粒。这款内存芯片遵循JEDEC设定的DDR3标准，确保了与行业兼容性。其关键特性包括： 1. **8n预取架构**：这意味着数据在每个时钟周期内被预取8次，提高了数据传输效率。 2. **差分时钟和数据 strobe**：使用CK/CK#和DQS/DQS#信号，这种设计能降低信号干扰，提高数据传输的准确性。 3. **双速率数据传输**：在DQs、DQSs和DM线上实现数据的双速率传输，进一步提升性能。 4. **数据完整性**：通过内置的温度传感器（TS）支持自动自刷新功能，确保在不同环境温度下的稳定性；自动刷新和自刷新模式可防止数据丢失。 5. **节能模式**：支持部分数组自刷新，只对当前活跃的内存阵列进行刷新，减少功耗；电源下降模式允许在不需要内存操作时降低功耗。 6. **CAS延迟**：提供了广泛的CAS延迟选择，从6到14，以适应不同的系统需求和性能优化。值得注意的是，默认情况下，部分阵列自刷新（PASR）是关闭的，需要通过电气熔丝启用，具体需求应咨询南亚科技。另外，如果工作温度超过85°C，需要外部执行2倍刷新速率，以保持内存的正常工作。违反tRFC规格可能导致功能异常。同时，该内存仅支持主要DQs的反馈，全DQs的反馈需通过电气熔丝启用，如有需求也应联系南亚科技。

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

Version 1.4 16 Nanya Technology Cooperation ©

MOD

Timing

CKE

MRS NOP NOP NOP NOPCMD

ADDR

tMOD

Non

MRS

VAL

Old Setting

Updating Setting

New Setting

VAL

Programming the Mode Registers (Cont’d)

The mode register contents can be changed using the same command and timing requirements during normal operation as

long as the DRAM is in idle state, i.e. all banks are in the precharged state with tRP satisfied, all data bursts are completed

and CKE is high prior to writing into the mode register. The mode registers are divided into various fields depending on the

functionality and/or modes.

Mode Register MR0

The mode-register MR0 stores data for controlling various operating modes of DDR3 (L) SDRAM. It controls burst length,

read burst type, CAS latency, test mode, DLL reset, WR, and DLL control for precharge Power-Down, which include

various vendor specific options to make DDR3(L) SDRAM useful for various applications. The mode register is written by

asserting low on , RA, A, WE, BA0, BA1, and BA2, while controlling the states of address pins according to the

following figure.

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

Version 1.4 18 Nanya Technology Cooperation ©

Burst Length, Type, and Order

Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via bit A3

as shown in the MR0 Definition as above figure. The ordering of access within a burst is determined by the burst length,

burst type, and the starting column address. The burst length is defined by bits A0-A1. Burst lengths options include fix BC4,

fixed BL8, and on the fly which allow BC4 or BL8 to be selected coincident with the registration of a Read or Write

command via A12/.

Burst Type and Burst Order

Burst

Length

Read

Write

Starting

Column

Address

(A2,A1,A0)

Burst type:

Sequential

(decimal)

A3 = 0

Burst type:

Interleaved

(decimal)

A3 = 1

Note

Chop

Read

0,0,0

0,1,2,3,T,T,T,T

1,2,3

0,0,1

1,2,3,0,T,T,T,T

1,0,3,2,T,T,T,T

0,1,0

2,3,0,1,T,T,T,T

0,1,1

3,0,1,2,T,T,T,T

3,2,1,0,T,T,T,T

1,0,0

4,5,6,7,T,T,T,T

1,0,1

5,6,7,4,T,T,T,T

5,4,7,6,T,T,T,T

1,1,0

6,7,4,5,T,T,T,T

1,1,1

7,4,5,6,T,T,T,T

7,6,5,4,T,T,T,T

Write

0,V,V

0,1,2,3,X,X,X,X

1,2,4,5

1,V,V

4,5,6,7,X,X,X,X

Read

0,0,0

0,1,2,3,4,5,6,7

0,0,1

1,2,3,0,5,6,7,4

1,0,3,2,5,4,7,6

0,1,0

2,3,0,1,6,7,4,5

0,1,1

3,0,1,2,7,4,5,6

3,2,1,0,7,6,5,4

1,0,0

4,5,6,7,0,1,2,3

1,0,1

5,6,7,4,1,2,3,0

5,4,7,6,1,0,3,2

1,1,0

6,7,4,5,2,3,0,1

1,1,1

7,4,5,6,3,0,1,2

7,6,5,4,3,2,1,0

Write

V,V,V

0,1,2,3,4,5,6,7

2,4

Note:

1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than the BL8

mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being selected

on-the-fly via A12/, the internal write operation starts at the same point in time like a burst of 8 write operation. This means that

during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.

2. 0~7 bit number is value of CA [2:0] that causes this bit to be the first read during a burst.

3. T: Output driver for data and strobes are in high impedance.

4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.

5. X: Do not Care.

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

CAS Latency

The CAS Latency is defined by MR0 (bit A9~A11) as shown in the MR0 Definition figure. CAS Latency is the delay, in

clock cycles, between the internal Read command and the availability of the first bit of output data. DDR3(L) SDRAM does

not support any half clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL) + CAS Latency

(CL); RL = AL + CL.

Test Mode

The normal operating mode is selected by MR0 (bit7=0) and all other bits set to the desired values shown in the MR0

definition figure. Programming bit A7 to a ‘1’ places the DDR3(L) SDRAM into a test mode that is only used by the DRAM

manufacturer and should not be used. No operations or functionality is guaranteed if A7=1.

DLL Reset

The DLL Reset bit is self-clearing, meaning it returns back to the value of ‘0’ after the DLL reset function has been issued.

Once the DLL is enabled, a subsequent DLL Reset should be applied. Anytime the DLL reset function is used, tDLLK

must be met before any functions that require the DLL can be used (i.e. Read commands or ODT synchronous

operations.)

Write Recovery

The programmed WR value MR0(bits A9, A10, and A11) is used for the auto precharge feature along with tRP to

determine tDAL WR (write recovery for auto-precharge)min in clock cycles is calculated by dividing tWR(ns) by tCK(ns)

and rounding up to the next integer: WRmin[cycles] = Roundup(tWR[ns]/tCK[ns]). The WR must be programmed to be

equal or larger than tWR (min).

Precharge PD DLL

MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12=0), or ‘slow-exit’,

the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit requires tXPDLL to be

met prior to the next valid command. When MR0 (A12=1), or ‘fast-exit’, the DLL is maintained after entering precharge

power-down and upon exiting power-down requires tXP to be met prior to the next valid command.

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