Stratix器件手册1：Altera公司技术详解

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"Stratix器件手册1" Stratix系列器件是Altera公司推出的一系列高性能FPGA（Field-Programmable Gate Array）芯片，主要应用于复杂数字逻辑设计和系统级集成。Stratix Device Handbook, Volume 1是Altera为开发者提供的一份详细的技术指南，涵盖了该系列器件的基本特性和使用方法。手册可能包含以下关键知识点： 1. **FPGA架构**：Stratix器件基于先进的工艺技术，具有高度可编程的逻辑单元、分布式存储器、I/O接口和嵌入式功能模块。这些组件构成了一种灵活的硬件平台，能够根据设计需求进行定制。 2. **逻辑单元**：Stratix FPGA的逻辑单元可能包括查找表（LUT）、乘法器、分布式RAM等，它们可以实现复杂的逻辑函数，并支持高速计算。 3. **嵌入式功能**：Stratix器件通常集成了如硬核处理器系统、PCI Express接口、DDR内存控制器、串行收发器等高级功能，这些嵌入式模块极大地简化了系统设计并提高了性能。 4. **I/O特性**：手册会详细介绍Stratix器件的输入输出特性，包括各种I/O标准的支持（如LVDS、HSTL、SSTL等），以及I/O速度等级、功耗管理和可配置性。 5. **设计流程**：从项目设置到编译、仿真、时序分析、布局布线，手册将提供完整的FPGA设计流程，帮助开发者理解如何利用Altera Quartus II等工具进行高效设计。 6. **功耗管理**：Stratix器件支持动态电压和频率调整（DVFS）、部分重配置等技术，以优化功耗并满足不同应用场合的需求。 7. **可靠性与稳定性**：手册会讨论Stratix器件的可靠性保证，包括温度范围、寿命预测、抗静电放电（ESD）保护等方面，确保在恶劣环境下也能稳定工作。 8. **知识产权（IP）保护**：Stratix FPGA的mask work rights和版权保护机制是确保设计安全的重要组成部分，手册可能涵盖如何保护设计免受非法复制和篡改。 9. **技术支持和更新**：Altera通常会提供持续的技术支持和产品更新，用户应定期查看最新的文档以获取最新的特性和改进。 10. **应用案例**：手册可能包含一些实际应用案例，展示Stratix器件在通信、计算、图像处理、航空航天等领域的成功应用。《Stratix Device Handbook, Volume 1》是FPGA开发者深入理解和有效利用Stratix器件的关键参考资料，它不仅提供了详尽的技术规格，还提供了设计指导和最佳实践，有助于开发者充分发挥Stratix FPGA的潜力。

1–6 Altera Corporation

Preliminary

Stratix Device Family Data Sheet Stratix Device Handbook, Volume 1

4 October 2003, v2.1

●

Added -8 speed grade information.

●

Updated performance information in Table 4–36.

●

Updated timing information in Tables 4–55 through 4–96.

●

Updated delay information in Tables 4–103 through 4–108.

●

Updated programmable delay information in Tables 4–100 and

4–103.

July 2003, v2.0

●

Updated clock rates in Tables 4–114 through 4–123.

●

Updated speed grade information in the introduction on page 4-1.

●

Corrected figures 4-1 & 4-2 and Table 4-9 to reflect how VID and VOD

are specified.

●

Added note 6 to Table 4-32.

●

Updated Stratix Performance Table 4-35.

●

Updated EP1S60 and EP1S80 timing parameters in Tables 4-82 to 4-

93. The Stratix timing models are final for all devices.

●

Updated Stratix IOE programmable delay chains in Tables 4-100 to 4-

101.

●

Added single-ended I/O standard output pin delay adders for loading

in Table 4-102.

●

Added spec for FPLL[10..7]CLK pins in Tables 4-104 and 4-107.

●

Updated high-speed I/O specification for J=2 in Tables 4-114 and 4-

115.

●

Updated EPLL specification and fast PLL specification in Tables 4-

116 to 4-120.

5 September 2004, v2.1

●

Updated reference to device pin-outs on page 5–1 to indicate that

device pin-outs are no longer included in this manual and are now

available on the Altera web site.

April 2003, v1.0

●

No new changes in Stratix Device Handbook v2.0.

Chapter Date/Version Changes Made

Altera Corporation 1–1

September 2004

1. Introduction

Introduction

The Stratix

family of FPGAs is based on a 1.5-V, 0.13-µm, all-layer copper

SRAM process, with densities of up to 79,040 logic elements (LEs) and up

to 7.5 Mbits of RAM. Stratix devices offer up to 22 digital signal

processing (DSP) blocks with up to 176 (9-bit × 9-bit) embedded

multipliers, optimized for DSP applications that enable efficient

implementation of high-performance filters and multipliers. Stratix

devices support various I/O standards and also offer a complete clock

management solution with its hierarchical clock structure with up to

420-MHz performance and up to 12 phase-locked loops (PLLs).

The following shows the main sections in the Stratix Device Family Data

Sheet:

Section Page

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1

Logic Array Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3

Logic Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6

MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14

TriMatrix Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21

Digital Signal Processing Block . . . . . . . . . . . . . . . . . . . . . . . . 2–52

PLLs & Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–73

I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–104

High-Speed Differential I/O Support. . . . . . . . . . . . . . . . . . 2–130

Power Sequencing & Hot Socketing . . . . . . . . . . . . . . . . . . . 2–141

IEEE Std. 1149.1 (JTAG) Boundary-Scan Support. . . . . . . . . . 3–1

SignalTap II Embedded Logic Analyzer . . . . . . . . . . . . . . . . . 3–5

Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–5

Temperature Sensing Diode. . . . . . . . . . . . . . . . . . . . . . . . . . . 3–13

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1

Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16

Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17

Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Device Pin-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–1

S51001-3.1

1–2 Altera Corporation

Stratix Device Handbook, Volume 1 September 2004

Features

The Stratix family offers the following features:

■

10,570 to 79,040 LEs; see Table 1–1

■

Up to 7,427,520 RAM bits (928,440 bytes) available without reducing

logic resources

■

TriMatrix

memory consisting of three RAM block sizes to

implement true dual-port memory and first-in first-out (FIFO)

buffers

■

High-speed DSP blocks provide dedicated implementation of

multipliers (faster than 300 MHz), multiply-accumulate functions,

and finite impulse response (FIR) filters

■

Up to 16 global clocks with 22 clocking resources per device region

■

Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device

provide spread spectrum, programmable bandwidth, clock switch-

over, real-time PLL reconfiguration, and advanced multiplication

and phase shifting

■

Support for numerous single-ended and differential I/O standards

■

High-speed differential I/O support on up to 116 channels with up

to 80 channels optimized for 840 megabits per second (Mbps)

■

Support for high-speed networking and communications bus

standards including RapidIO, UTOPIA IV, CSIX, HyperTransport

technology, 10G Ethernet XSBI, SPI-4 Phase 2 (POS-PHY Level 4),

and SFI-4

■

Differential on-chip termination support for LVDS

■

Support for high-speed external memory, including zero bus

turnaround (ZBT) SRAM, quad data rate (QDR and QDRII) SRAM,

double data rate (DDR) SDRAM, DDR fast cycle RAM (FCRAM),

and single data rate (SDR) SDRAM

■

Support for 66-MHz PCI (64 and 32 bit) in -6 and faster speed-grade

devices, support for 33-MHz PCI (64 and 32 bit) in -8 and faster

speed-grade devices

■

Support for 133-MHz PCI-X 1.0 in -5 speed-grade devices

■

Support for 100-MHz PCI-X 1.0 in -6 and faster speed-grade devices

■

Support for 66-MHz PCI-X 1.0 in -7 speed-grade devices

■

Support for multiple intellectual property megafunctions from

Altera MegaCore

functions and Altera Megafunction Partners

Program (AMPP

) megafunctions

■

Support for remote configuration updates

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