NXP i.MX RT1170 高性能处理器数据手册

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"NXP-MIMXRT1175AVM8A.pdf 是NXP半导体公司的一款基于i.MX RT系列的微处理器的数据手册。该手册涵盖了MIMXRT1176DVMAA、MIMXRT1175DVMAA、MIMXRT1172DVMAA和MIMXRT1171DVMAA等型号的详细技术数据。处理器主要特点是内置高性能的Arm Cortex-M7核心，工作频率可达1GHz，以及一个节能的Cortex-M4核心，最高运行速度为400MHz。" 在这款微处理器中，NXP采用了先进的Cortex-M7内核设计，它能够以高达1GHz的速度运行，提供了强大的处理能力。此外，还有一个Cortex-M4内核，其最大工作频率为400MHz，适用于低功耗场景。这样的双核配置使得i.MX RT1170在性能和能效之间找到了良好的平衡。处理器配备了总计2MB的片上RAM，其中包括768KB的RAM，这部分内存可以灵活配置，既可以作为与M7内核共享的512KB TCM（ Tight Coupled Memory），也可以作为与M4内核共享的256KB TCM，或者用作通用片上RAM。这种内存配置方式增加了系统的灵活性，适应了不同的应用需求。电源管理是i.MX RT1170的另一个亮点。它集成了高级电源管理模块，包括DC-DC转换器和LDO稳压器，减少了外部电源的复杂性，并简化了电源排序过程，有助于优化系统整体的能耗表现。除此之外，该处理器提供多种内存接口，如SDRAM、RAW NAND FLASH、NOR FLASH、SD/eMMC、Quad/Octal SPI、Hyper RAM/Flash等，这使得它可以轻松连接各种类型的存储设备，扩大了其在嵌入式系统中的应用范围。同时，它还支持一系列其他接口，表明其具有广泛的外设兼容性和扩展能力。总结来说，NXP的MIMXRT117x系列微处理器是一款高效能、低功耗的解决方案，适用于需要高性能计算能力和丰富接口选择的嵌入式应用，如工业自动化、物联网(IoT)设备、消费电子产品等。通过其灵活的内存配置和强大的外设支持，开发者能够构建出满足各种需求的高性能系统。

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i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 12/2020

16 NXP Semiconductors

Modules list

LPUART1

LPUART2

LPUART3

LPUART4

LPUART5

LPUART6

LPUART7

LPUART8

LPUART9

LPUART10

LPUART11

LPUART12

UART Interface Connectivity

Peripherals

Each of the UART modules support the following serial

data transmit/receive protocols and configurations:

• 7- or 8-bit data words, 1 or 2 stop bits, programmable

parity (even, odd or none)

• Programmable baud rates up to 5 Mbps.

MECC64 Error Correcting Code Memories and

Memory Controllers

MECC64 module supports Single Error Correction and

Double Error Detection (SECDED) ECC function to

provide reliability for 4 banks On-Chip RAM (OCRAM)

access. When ECC function is disabled, ECC OCRAM

can be also used to store data.

MIPI-CSI MIPI CSI Interface Multimedia

Peripherals

Key features of MIPI CSI controller are listed as

following:

• Implements all three MIPI CSI-2 layers

• Supports CSI-2 Unidirectional Master operation

• Virtual Channel support

• Flexible pixel-based user interface

MIPI-DSI MIPI DSI Interface Multimedia

Peripherals

Key features of MIPI DSI controller are listed as

following:

• Implements all three DSI layers

• Supports Command and Video Modes

• Virtual Channel support

• Flexible packet based user interface

MQS Medium Quality Sound Multimedia

Peripherals

MQS is used to generate 2-channel medium quality

PWM-like audio via two standard digital GPIO pins.

MU Messaging Unit System Control The Messaging Unit module enables two processors

within the SoC to communicate and coordinate by

passing messages (e.g. data, status, and control)

through the MU interface.

The MU also provides the ability for one processor to

signal the other processor using interrupts.

Table 3. i.MX RT1170 modules list (continued)

Block Mnemonic Block Name Subsystem Brief Description

Modules list

i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 12/2020

NXP Semiconductors 17

OCOTP_CTRL OTP Controller Security The On-Chip OTP controller (OCOTP_CTRL) provides

an interface for reading, programming, and/or overriding

identification and control information stored in on-chip

fuse elements. The module supports electrically

programmable poly fuses (eFUSEs). The

OCOTP_CTRL also provides a set of volatile

software-accessible signals that can be used for

software control of hardware elements, not requiring

non volatility. The OCOTP_CTRL provides the primary

user-visible mechanism for interfacing with on-chip fuse

elements. Among the uses for the fuses are unique chip

identifiers, mask revision numbers, cryptographic keys,

JTAG secure mode, boot characteristics, and various

control signals requiring permanent non volatility.

OCRAM On-Chip Memory

controller

Memories and

Memory Controllers

The On-Chip Memory controller (OCRAM) module is

designed as an interface between the system’s AXI bus

and the internal (on-chip) SRAM memory module.

In i.MX 8M Plus processors, the OCRAM is used for

controlling the 868KB multimedia RAM through AXI

bus.

OSC Oscillator Clock Sources and

Control

Two crystal oscillators:

• 48 MHz crystal oscillator: it is used as primary clock

source for all the PLLs to generate the clock for CPU,

BUS, and high-speed interfaces.

• 32 kHz crystal oscillator: it is the primary clock source

for RTC as well as low speed clock source for

CCM/SRC/GPC.

PDM Pulse Density Modulation Multimedia

Peripherals

The PDM supports up to 8-channels (4 lanes) digital

MIC inputs.

PIT1

PIT2

Periodical Interrupt Timer Timer Peripherals The PIT features 32-bit counter timer, programmable

count modules, clock division features, interrupt

generation, and a slave mode to synchronize count

enable for multiple PITs.

PXP Pixel Processing Pipeline Multimedia

Peripherals

A high-performance pixel processor capable of 1

pixel/clock performance for combined operations, such

as color-space conversion, alpha blending, and rotation.

The PXP is enhanced

with features specifically for gray scale applications. In

addition, the PXP supports traditional pixel/frame

processing paths for still-image and video processing

applications.

Quadrature DEC1

Quadrature DEC2

Quadrature DEC3

Quadrature DEC4

Quadrature Decoder Timer Peripherals The enhanced quadrature decoder module provides

interfacing capability to position/speed sensors. There

are five input signals: PHASEA, PHASEB, INDEX,

TRIGGER, and HOME. This module is used to decode

shaft position, revolution count, and speed.

Table 3. i.MX RT1170 modules list (continued)

Block Mnemonic Block Name Subsystem Brief Description

i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 12/2020

18 NXP Semiconductors

Modules list

QuadTimer1

QuadTimer2

QuadTimer3

QuadTimer4

QuadTimer Timer Peripherals The quad-timer provides four time channels with a

variety of controls affecting both individual and

multi-channel features.Specific features include

up/down count, cascading of counters, programmable

module, count once/repeated, counter preload,

compare registers with preload, shared use of input

signals, prescaler controls, independent

capture/compare, fault input control, programmable

input filters, and multi-channel synchronization.

RDC Resource Domain

Controller

Security The RDC provides robust support for the isolation of

processing domain to prevent one core from accessing

another’s peripherals, to control access rights to

common memory and provide hardware enforcement of

semaphore based locking of shared peripherals.

For single system use case, RDC can be disabled and

AIPS-TZ/DEXSC can be bypassed. For dual system

case, RDC can be configured and locked each core

starts their own image.

ROMCP ROM Controller with

Patch

Memories and

Memory Controllers

The ROMCP acts as an interface between the Arm

advanced high-performance bus and the ROM. The

on-chip ROM is only used by the Cortex-M7 core during

boot up. Size of the ROM is 256 KB.

RTC OSC Real Time Clock

Oscillator

Clock Sources and

Control

The RTC OSC provides the clock source for the

Real-Time Clock module. The RTC OSC module, in

conjunction with an external crystal, generates a 32.678

kHz reference clock for the RTC.

SAI1

SAI2

SAI3

SAI4

Synchronous Audio

Interface

Multimedia

Peripherals

The SAI module provides a synchronous audio interface

(SAI) that supports full duplex serial interfaces with

frame synchronization, such as I2S, AC97, TDM, and

codec/DSP interfaces.

SEMA4 Semaphores System Control The SEMA4 module implements hardware-enforced

semaphores as an IPS-mapped slave peripheral device

and provides 16 hardware-enforced gates in a

dual-processor configuration.

SEMC Smart External Memory

Controller

Memory and

Memory Controller

The SEMC is a multi-standard memory controller

optimized for both high-performance and low pin-count.

It can support multiple external memories in the same

application with shared address and data pins. The

interface supported includes SDRAM, NOR Flash,

SRAM, and NAND Flash, as well as 8080 display

interface.

SNVS Secure Non-Volatile

Storage

Security Secure Non-Volatile Storage, including Secure Real

Time Clock, Security State Machine, Master Key

Control, and Violation/Tamper Detection and reporting.

SPDIF Sony Philips Digital

Interconnect Format

Multimedia

Peripherals

A standard audio file transfer format, developed jointly

by the Sony and Phillips corporations. Has Transmitter

and Receiver functionality.

Table 3. i.MX RT1170 modules list (continued)

Block Mnemonic Block Name Subsystem Brief Description

Modules list

i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 12/2020

NXP Semiconductors 19

SSARC State Save and Restore

Controller

Memories and

Memory Controllers

The SSARC saves the registers of functional modules in

memory before power down, and restores registers from

memory after the module is powered up.

TEMP SENSE Temperature Sensor Analog The temperature sensor implements a temperature

sensor/conversion function based on a

temperature-dependent voltage to time conversion.

USB1

USB2

Universal Serial Bus 2.0 Connectivity

Peripherals

USB 2.0 OTG modules (USB OTG1 and USB OTG2)

contains:

• Two high-speed OTG 2.0 modules with integrated HS

USB PHYs

• Support eight Transmit (TX) and eight Receive (Rx)

endpoints, including endpoint 0

uSDHC1

uSDHC2

SD/MMC and SDXC

Enhanced Multi-Media

Card / Secure Digital Host

Controller

Connectivity

Peripherals

i.MX RT1170 specific SoC characteristics:

All four MMC/SD/SDIO controllers are identical and are

based on the uSDHC. They are:

• Fully compliant with MMC command/response sets

and Physical Layer as defined in the Multimedia Card

System Specification, v4.5/4.2/4.3/4.4/4.41/ including

high-capacity (size > 2 GB) cards HC MMC.

• Fully compliant with SD command/response sets and

Physical Layer as defined in the SD Memory Card

Specifications, v3.0 including high-capacity SDXC

cards up to 2 TB.

• Fully compliant with SDIO command/response sets

and interrupt/read-wait mode as defined in the SDIO

Card Specification, Part E1, v3.0

Two ports support:

• 1-bit or 4-bit transfer mode specifications for SD and

SDIO cards up to UHS-I SDR104 mode (104 MB/s

max)

• 1-bit, 4-bit, or 8-bit transfer mode specifications for

MMC cards up to 52 MHz in both SDR and DDR

modes (104 MB/s max)

• 4-bit or 8-bit transfer mode specifications for eMMC

chips up to 200 MHz in HS200 mode (200 MB/s max)

VIDMUX Video mux Mux control Video mux are mux control for Parallel CSI (IO PADs),

MIPI CSI-2, MIPI DSI, Parallel LCDIF (IO PADs) and

CSI, LCDIF-V2, eLCDIF control. It also includes the

DCIC of MIPI DSI and Parallel DSI.

Table 3. i.MX RT1170 modules list (continued)

Block Mnemonic Block Name Subsystem Brief Description

i.MX RT1170 Crossover Processors Data Sheet for Consumer Products, Rev. 0, 12/2020

20 NXP Semiconductors

Modules list

3.1 Special signal considerations

Table 4 lists special signal considerations for the i.MX RT1170 processors. The signal names are listed in

alphabetical order.

The package contact assignments can be found in Section 6, Package information and contact

assignments.” Signal descriptions are provided in the i.MX RT1170 Reference Manual

(IMXRT1170RM).

WDOG1

WDOG2

WDOG3

WDOG4

Watch Dog Timer Peripherals WDOG1 and WDOG2 Timer support two comparison

points during each counting period. Each of the

comparison points is configurable to evoke an interrupt

to the Arm core, and a second point evokes an external

event on the WDOG line.

WDOG3 and WDOG4 modules are high reliability

independent timers that are available for system to use.

They provide a safety feature to ensure software is

executing as planned and the CPU is not stuck in an

infinite loop or executing unintended code. If the WDOG

module is not serviced (refreshed) within a certain

period, it resets the MCU. Windowed refresh mode is

supported as well.

XBARA

XBARB

Cross BAR Cross Trigger Each crossbar switch is an array of muxes with shared

inputs. Each mux output provides one output of the

crossbar. The number of inputs and the number of

muxes/outputs are user configurable and registers are

provided to select which of the shared inputs are routed

to each output.

XECC External ECC Controller Memories and

Memory Controllers

XECC can be used as a gasket module on AXI bus to

support ECC function for external memory.

XRDC Extended Resource

Domain Controller

Security The XRDC provides an integrated, scalable

architectural framework for access control, system

memory protection, and peripheral isolation. It allows

software to assign chip resources including processor

cores, non-core bus masters, memory regions, and

slave peripherals to processing domains to support

enforcement of robust operational environments.

Table 4. Special signal considerations

Signal Name Remarks

CLK1_P/ CLK1_N It is used only for internal test, please make CLK1_N/P pairs remain unconnected.

DCDC_PSWITCH PAD is in DCDC_IN domain and connected the ground to bypass DCDC.

To enable DCDC function, assert to DCDC_IN with at least 1ms delay for DCDC_IN rising edge.

Table 3. i.MX RT1170 modules list (continued)

Block Mnemonic Block Name Subsystem Brief Description

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NXP i.MX RT1170 高性能处理器数据手册

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