verilog编程电子秒表实验如何驱动六位数码管，如何控制数码小数点的亮灭

要控制数码管小数点的亮灭，可以在数码管的显示芯片中设置相应的位来控制小数点的显示。具体的实现方式可以参考数码管显示芯片的数据手册。

下面是一个示例Verilog程序，可以实现六位数码管的驱动，并控制小数点的亮灭：

module six_digit_display(
  input clk,
  input rst,
  input [23:0] data,
  input dp_en,

  output reg [5:0] seg,
  output reg [5:0] an,
  output reg dp
);

reg [3:0] cnt = 4'b0000;
reg [23:0] num = 24'd0;

always @(posedge clk) begin
  if (rst) begin
    cnt <= 4'b0000;
    num <= 24'd0;
  end else begin
    cnt <= cnt + 1;
    if (cnt == 4'b1000) cnt <= 4'b0000;

    case (cnt)
      4'b0001: begin
        num[3:0] <= data[3:0];
        an <= 6'b111111;
      end
      4'b0010: begin
        num[7:4] <= data[7:4];
        an <= 6'b111110;
      end
      4'b0100: begin
        num[11:8] <= data[11:8];
        an <= 6'b111101;
      end
      4'b1000: begin
        num[15:12] <= data[15:12];
        an <= 6'b111011;
      end
      4'b0000: begin
        num[19:16] <= data[19:16];
        an <= 6'b110111;
      end
      4'b0011: begin
        num[23:20] <= data[23:20];
        an <= 6'b101111;
      end
      default: begin
        num <= 24'd0;
        an <= 6'b111111;
      end
    endcase
  end
end

always @(num) begin
  case (num)
    24'd0: seg <= 6'b100000;
    24'd1: seg <= 6'b111100;
    24'd2: seg <= 6'b010010;
    24'd3: seg <= 6'b011000;
    24'd4: seg <= 6'b001100;
    24'd5: seg <= 6'b001001;
    24'd6: seg <= 6'b000001;
    24'd7: seg <= 6'b111100;
    24'd8: seg <= 6'b000000;
    24'd9: seg <= 6'b001100;
    default: seg <= 6'b100000;
  endcase
  
  if (dp_en) begin
    dp <= 1'b1;
  end else begin
    dp <= 1'b0;
  end
end

endmodule

在这个例子中，我们增加了一个输入端口 `dp_en`，用来控制小数点的亮灭。当 `dp_en` 为高电平时，我们将 `dp` 输出为低电平，以控制数码管小数点的亮灭。在其他时间，我们将 `dp` 输出为高电平，以防止数码管小数点的显示。