用16Kx8 位的 DRAM 芯片构成64Kx32位存储器，请画出该存储器的组成逻辑框图

由于该存储器需要64Kx32位，可以采用4片16Kx8位的DRAM芯片构成，其中每片DRAM芯片需要16K地址线和8位数据线。

下面是该存储器的组成逻辑框图：

                             +-------+       +-------+
address lines 0-13  ----------|DRAM 0|------>|       |
                             |       |       |       |
address lines 14-15 --->     +-------+       |       |
                                           |       |
                                           +-------+

                             +-------+       +-------+
address lines 0-13  ----------|DRAM 1|------>|       |
                             |       |       |       |
address lines 14-15 --->     +-------+       |       |
                                           |       |
                                           +-------+

                             +-------+       +-------+
address lines 0-13  ----------|DRAM 2|------>|       |
                             |       |       |       |
address lines 14-15 --->     +-------+       |       |
                                           |       |
                                           +-------+

                             +-------+       +-------+
address lines 0-13  ----------|DRAM 3|------>|       |
                             |       |       |       |
address lines 14-15 --->     +-------+       |       |
                                           |       |
                                           +-------+

                           +---+ +---+ +---+ +---+
data lines 0-7   ---------->|   | |   | |   | |   |
                           +---+ +---+ +---+ +---+

                           +---+ +---+ +---+ +---+
data lines 8-15  ---------->|   | |   | |   | |   |
                           +---+ +---+ +---+ +---+

                           +---+ +---+ +---+ +---+
data lines 16-23 ---------->|   | |   | |   | |   |
                           +---+ +---+ +---+ +---+

                           +---+ +---+ +---+ +---+
data lines 24-31 ---------->|   | |   | |   | |   |
                           +---+ +---+ +---+ +---+

其中，每个DRAM芯片的地址线0至地址线13连接到存储器地址总线的0至13位，地址线14和地址线15输入时序生成器，用于产生DRAM芯片的行地址和列地址信号；每个DRAM芯片的8位数据输出连接到存储器的数据总线上的8位至31位。由于每个DRAM芯片的8位输出是串联在一起的，需要通过一个复用器将字节选通到数据总线上的对应位。