用Verilog 描述能够产生序列信号的序列信号产生器，写出代码。

module seq_gen(
input clk,
input rst,
output reg seq_out
);

reg [3:0] count;

always @(posedge clk or negedge rst) begin
if(!rst) begin
count <= 4'b0000;
seq_out <= 1'b0;
end else begin
count <= count + 1;
case(count)
4'b0000: seq_out <= 1'b0;
4'b0001: seq_out <= 1'b1;
4'b0010: seq_out <= 1'b0;
4'b0011: seq_out <= 1'b1;
4'b0100: seq_out <= 1'b0;
4'b0101: seq_out <= 1'b1;
4'b0110: seq_out <= 1'b0;
4'b0111: seq_out <= 1'b1;
4'b1000: seq_out <= 1'b0;
4'b1001: seq_out <= 1'b1;
4'b1010: seq_out <= 1'b0;
4'b1011: seq_out <= 1'b1;
4'b1100: seq_out <= 1'b0;
4'b1101: seq_out <= 1'b1;
4'b1110: seq_out <= 1'b0;
4'b1111: seq_out <= 1'b1;
endcase
end
end

endmodule