用Verilog 描述能够产生“1101000101序列信号的序列信号产生器，写出代码

module seq_gen(
input clk,
output reg out
);

reg [9:0] count;

always @(posedge clk) begin
if (count == 10'b1101000101) begin
count <= 0;
out <= ~out;
end else begin
count <= {count[8:0], count[9]};
end
end

endmodule