用 8 位数控分频器设计 16 位数控分频器的vhdl语言

entity divider16 is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
out_16 : out STD_LOGIC);
end divider16;

architecture Behavioral of divider16 is

signal count : integer range 0 to 7 := 0;
signal out_8 : STD_LOGIC;

component divider8 is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
out_8 : out STD_LOGIC);
end component;

begin

divide8: divider8 port map(clk, reset, out_8);

process(clk, reset)
begin
if reset = '1' then
count <= 0;
out_16 <= '0';
elsif rising_edge(clk) then
if count = 7 then
count <= 0;
out_16 <= not out_16;
else
count <= count + 1;
end if;
end if;
end process;

end Behavioral;