verilog中取余

在Verilog中，取余运算可以通过使用除法算法来实现。下面是一个Verilog HDL代码的例子:

module div_rill (input [31:0 a, input [31:0 b, output reg [31:0 yshang, output reg [31:0 yyushu);
  reg [31:0 tempa;
  reg [31:0 tempb;
  reg [63:0 temp_a;
  reg [63:0 temp_b;
  integer i;
  
  always @(a or b) begin
    tempa <= a;
    tempb <= b;
  end
  
  always @(tempa or tempb) begin
    temp_a = {32'h00000000, tempa};
    temp_b = {tempb, 32'h00000000};
    
    for (i = 0; i < 32; i = i + 1) begin
      temp_a = {temp_a >= tempb)
        temp_a = temp_a - temp_b + 1'b1;
      else
        temp_a = temp_a;
    end
    
    yshang <= temp_a<span class="em">1</span><span class="em">2</span><span class="em">3</span>
#### 引用[.reference_title]
-  *1* [快速幂以及取余](https://blog.csdn.net/glancelike/article/details/104342740)[target="_blank" data-report-click={"spm":"1018.2226.3001.9630","extra":{"utm_source":"vip_chatgpt_common_search_pc_result","utm_medium":"distribute.pc_search_result.none-task-cask-2~all~insert_cask~default-1-null.142^v93^chatsearchT3_1"}}] [.reference_item style="max-width: 50%"]
-  *2* *3* [FPGA的快速除法及取余运算(Verilog)](https://blog.csdn.net/weixin_43813325/article/details/121399973)[target="_blank" data-report-click={"spm":"1018.2226.3001.9630","extra":{"utm_source":"vip_chatgpt_common_search_pc_result","utm_medium":"distribute.pc_search_result.none-task-cask-2~all~insert_cask~default-1-null.142^v93^chatsearchT3_1"}}] [.reference_item style="max-width: 50%"]
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