dsp28335epwm互补带死区 DEMO

以下是DSP28335 EPWM模块互补带死区的一个简单DEMO示例：

#include "DSP2833x_Device.h"
#include "DSP2833x_Examples.h"

void InitEPwm1(void);
void InitEPwm2(void);
void InitEPwm3(void);

void main(void)
{
    InitSysCtrl();

    DINT;

    InitPieCtrl();

    IER = 0x0000;
    IFR = 0x0000;

    InitPieVectTable();

    InitEPwm1();
    InitEPwm2();
    InitEPwm3();

    EINT;

    ERTM;

    while(1);
}

void InitEPwm1(void)
{
    EPwm1Regs.TBPRD = 600;     // Set period to 600 TBCLK counts
    EPwm1Regs.TBPHS.bit.TBPHS = 0;   // Phase is 0
    EPwm1Regs.TBCTR = 0;       // Clear counter

    EPwm1Regs.CMPA.half.CMPA = 300;  // Set duty cycle to 50%
    EPwm1Regs.CMPB = 300;      // Set duty cycle to 50%

    EPwm1Regs.AQCTLA.bit.PRD = AQ_SET;   // Set PWM1A on period
    EPwm1Regs.AQCTLA.bit.CAU = AQ_CLEAR;    // Clear PWM1A on CMPA up
    EPwm1Regs.AQCTLB.bit.PRD = AQ_SET;   // Set PWM1B on period
    EPwm1Regs.AQCTLB.bit.CBU = AQ_CLEAR;    // Clear PWM1B on CMPB up

    EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // Enable dead-band
    EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;    // Active high complementary
    EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;   // EPWMxA is source for both falling/rising edge delay
    EPwm1Regs.DBRED = 50;       // Falling edge delay = 50 TBCLKs
    EPwm1Regs.DBFED = 50;       // Rising edge delay = 50 TBCLKs

    EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;   // Count up
    EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;  // Disable phase loading
    EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
    EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV1;   // Clock ratio to SYSCLKOUT
}

void InitEPwm2(void)
{
    EPwm2Regs.TBPRD = 600;     // Set period to 600 TBCLK counts
    EPwm2Regs.TBPHS.bit.TBPHS = 0;   // Phase is 0
    EPwm2Regs.TBCTR = 0;       // Clear counter

    EPwm2Regs.CMPA.half.CMPA = 300;  // Set duty cycle to 50%
    EPwm2Regs.CMPB = 300;      // Set duty cycle to 50%

    EPwm2Regs.AQCTLA.bit.PRD = AQ_SET;   // Set PWM2A on period
    EPwm2Regs.AQCTLA.bit.CAU = AQ_CLEAR;    // Clear PWM2A on CMPA up
    EPwm2Regs.AQCTLB.bit.PRD = AQ_SET;   // Set PWM2B on period
    EPwm2Regs.AQCTLB.bit.CBU = AQ_CLEAR;    // Clear PWM2B on CMPB up

    EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // Enable dead-band
    EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;    // Active high complementary
    EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;   // EPWMxA is source for both falling/rising edge delay
    EPwm2Regs.DBRED = 50;       // Falling edge delay = 50 TBCLKs
    EPwm2Regs.DBFED = 50;       // Rising edge delay = 50 TBCLKs

    EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;   // Count up
    EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE;  // Disable phase loading
    EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
    EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV1;   // Clock ratio to SYSCLKOUT
}

void InitEPwm3(void)
{
    EPwm3Regs.TBPRD = 600;     // Set period to 600 TBCLK counts
    EPwm3Regs.TBPHS.bit.TBPHS = 0;   // Phase is 0
    EPwm3Regs.TBCTR = 0;       // Clear counter

    EPwm3Regs.CMPA.half.CMPA = 300;  // Set duty cycle to 50%
    EPwm3Regs.CMPB = 300;      // Set duty cycle to 50%

    EPwm3Regs.AQCTLA.bit.PRD = AQ_SET;   // Set PWM3A on period
    EPwm3Regs.AQCTLA.bit.CAU = AQ_CLEAR;    // Clear PWM3A on CMPA up
    EPwm3Regs.AQCTLB.bit.PRD = AQ_SET;   // Set PWM3B on period
    EPwm3Regs.AQCTLB.bit.CBU = AQ_CLEAR;    // Clear PWM3B on CMPB up

    EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE; // Enable dead-band
    EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;    // Active high complementary
    EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;   // EPWMxA is source for both falling/rising edge delay
    EPwm3Regs.DBRED = 50;       // Falling edge delay = 50 TBCLKs
    EPwm3Regs.DBFED = 50;       // Rising edge delay = 50 TBCLKs

    EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UP;   // Count up
    EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE;  // Disable phase loading
    EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV1; // Clock ratio to SYSCLKOUT
    EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV1;   // Clock ratio to SYSCLKOUT
}

该示例通过初始化三个EPWM模块来实现互补带死区输出。在每个EPWM模块中，设置了一个周期为600 TBCLK计数的PWM信号，并且通过设置相应的寄存器来启用互补模式和带死区功能。其中，`EPwm1Regs`、`EPwm2Regs`、`EPwm3Regs`分别表示三个EPWM模块的寄存器组。