round robin 5路verilog实现 与tb文件
时间: 2023-08-23 13:06:39 浏览: 88
以下是Round Robin 5路 Verilog 实现的代码和测试台文件:
```
// Round Robin 5路 Verilog 实现
module round_robin_5(input clk,
input reset,
input [4:0] request,
output reg [4:0] grant);
reg [4:0] priority;
reg [2:0] round;
always @(posedge clk) begin
if (reset) begin
priority <= 5'b11111;
round <= 3'b0;
end else begin
priority <= {priority[3:0], priority[4]};
if (request != 0) priority[0] <= 1'b0;
if (priority == 5'b00000) priority <= 5'b11111;
if (round == 3'b0) begin
if (priority[0]) grant <= 1'b1;
round <= 3'b1;
end else if (round == 3'b1) begin
if (priority[1]) grant <= 1'b1;
round <= 3'b2;
end else if (round == 3'b2) begin
if (priority[2]) grant <= 1'b1;
round <= 3'b3;
end else if (round == 3'b3) begin
if (priority[3]) grant <= 1'b1;
round <= 3'b4;
end else begin
if (priority[4]) grant <= 1'b1;
round <= 3'b0;
end
end
end
endmodule
```
```
// Round Robin 5路 Verilog 测试台文件
`timescale 1ns / 1ns
module round_robin_5_tb();
reg clk, reset;
reg [4:0] request;
wire [4:0] grant;
round_robin_5 dut(
.clk(clk),
.reset(reset),
.request(request),
.grant(grant)
);
initial begin
clk = 1'b0;
reset = 1'b1;
request = 5'b11111;
#10 reset = 1'b0;
#10 request = 5'b00001;
#10 request = 5'b00010;
#10 request = 5'b00100;
#10 request = 5'b01000;
#10 request = 5'b10000;
#10 request = 5'b00000;
#10 request = 5'b10101;
#10 request = 5'b01010;
#10 request = 5'b00101;
#10 request = 5'b10010;
#10 request = 5'b01001;
#10 request = 5'b00000;
#10 request = 5'b10101;
#10 request = 5'b01010;
#10 request = 5'b00101;
#10 request = 5'b10010;
#10 request = 5'b01001;
#10 request = 5'b00000;
#10 $finish;
end
always #5 clk = ~clk;
endmodule
```
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