用case实现round robin 4路verilog实现 与tb文件

以下是Round Robin 4路Verilog实现：

module round_robin_4(input clk, input reset, input [3:0] request, output reg [3:0] grant);

reg [1:0] counter;

always @(posedge clk) begin
    if (reset) begin
        counter <= 2'b00;
        grant <= 4'b0001;
    end
    else begin
        // Check for requests
        if (request != 4'b0000) begin
            // Load counter
            counter <= counter + 2'b01;
            // Check for overflow
            if (counter == 2'b11) begin
                counter <= 2'b00;
            end
            // Check for requests
            if (request[counter]) begin
                grant <= {grant[2:0], grant[3]};
            end
        end
    end
end

endmodule

以下是Round Robin 4路Testbench文件：

`timescale 1ns / 1ps

module round_robin_4_tb;

reg clk;
reg reset;
reg [3:0] request;
wire [3:0] grant;

round_robin_4 dut (
    .clk(clk),
    .reset(reset),
    .request(request),
    .grant(grant)
);

initial begin
    clk = 0;
    reset = 1;
    request = 4'b0000;
    #10 reset = 0;
    #10 request = 4'b0001;
    #10 request = 4'b0010;
    #10 request = 4'b0100;
    #10 request = 4'b1000;
    #10 request = 4'b0011;
    #10 request = 4'b0110;
    #10 request = 4'b1100;
    #10 request = 4'b1010;
    #10 request = 4'b1111;
    #10 request = 4'b0000;
    #10 $finish;
end

always #5 clk = ~clk;

endmodule

在testbench中，我们将request信号逐个设置为4个输入端口的请求。您可以根据需要更改此测试向量。