首页Error-[SE] Syntax error Following verilog source has syntax error : "/ic/projects/BM2020_N22/users/dazhi.du/new1/BM2020_N22/1_rtl_rvn/5_core_logic/6_rvn_new/cdag_read.v", 131: token is 'endmodule'

Error-[SE] Syntax error Following verilog source has syntax error : "/ic/projects/BM2020_N22/users/dazhi.du/new1/BM2020_N22/1_rtl_rvn/5_core_logic/6_rvn_new/cdag_read.v", 131: token is 'endmodule'

时间: 2023-08-12 10:03:34 浏览: 413

Syntax Error

这个错误提示是Verilog代码中的语法错误，错误出现在文件"/ic/projects/BM2020_N22/users/dazhi.du/new1/BM2020_N22/1_rtl_rvn/5_core_logic/6_rvn_new/cdag_read.v"的第131行，错误标识符是"endmodule"。这个错误通常是由于代码中缺失了必要的语法元素或者语法结构不正确所导致的。你需要检查代码的语法，确保代码中所有的语法元素都被正确地使用，并且所有的语法结构都被正确地嵌套。你还可以使用Verilog语法检查工具来查找和解决语法错误。

Error-[SE] Syntax error Following verilog source has syntax error : "/ic/projects/BM2020_N22/users/dazhi.du/new1/BM2020_N22/1_rtl_rvn/5_core_logic/6_rvn_new/cdag_read.v", 131: token is 'endmodule'

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Error: arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts:22.13-19 syntax error FATAL ERROR: Unable to parse input tree make[1]: * [scripts/Makefile.lib:296：arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dtb] 错误 1 make: * [Makefile:1277：suniv-f1c100s-licheepi-nano.dtb] 错误 2