verilog的qpsk的costas环，IQ分别先经过降采样模块，再经过鉴相器计算相差，再通过环路滤波器输出32位的频率控制字

Verilog代码如下：

// 降采样模块
module downsample(
input clk,
input [1:0] in,
output reg [1:0] out,
parameter N = 4 // 降采样因子
);
reg [1:0] buf [0:N-1];
reg [1:0] cnt;

always @(posedge clk) begin
buf[cnt] <= in;
cnt <= (cnt == N-1) ? 0 : cnt + 1;
end

assign out = buf[0];
endmodule

// 鉴相器模块
module phase_detector(
input clk,
input [1:0] i,
input [1:0] q,
input [31:0] freq_word_in,
output reg [31:0] freq_word_out
);
reg [1:0] i_buf, q_buf;
reg [31:0] freq_word_buf;

always @(posedge clk) begin
// 更新频率控制字
freq_word_buf <= freq_word_in + ((i_buf * q) - (q_buf * i)) * 2;
freq_word_out <= freq_word_buf;

// 更新IQ样本
i_buf <= i;
q_buf <= q;
end
endmodule

// 环路滤波器模块
module loop_filter(
input clk,
input [31:0] freq_word_in,
output reg [31:0] freq_word_out,
parameter Kp = 32'd100, // 比例增益
Ki = 32'd1 // 积分增益
);
reg [31:0] freq_word_buf;
reg [31:0] integrator;

always @(posedge clk) begin
// 更新频率控制字
freq_word_buf <= freq_word_in + Kp * freq_word_in + Ki * integrator;
freq_word_out <= freq_word_buf;

// 更新积分器
integrator <= integrator + freq_word_in;
end
endmodule

// Costas环模块
module costas_loop(
input clk,
input [1:0] i_in,
input [1:0] q_in,
output reg [31:0] freq_word
);
reg [1:0] i_down, q_down;
reg [31:0] freq_word_buf;

downsample ds_i(.clk(clk), .in(i_in), .out(i_down)); // I分量降采样
downsample ds_q(.clk(clk), .in(q_in), .out(q_down)); // Q分量降采样
phase_detector pd(.clk(clk), .i(i_down), .q(q_down), .freq_word_in(freq_word_buf), .freq_word_out(freq_word_buf)); // 鉴相器
loop_filter lf(.clk(clk), .freq_word_in(freq_word_buf), .freq_word_out(freq_word), .Kp(32'd100), .Ki(32'd1)); // 环路滤波器

always @(posedge clk) begin
freq_word_buf <= freq_word; // 更新频率控制字
end
endmodule

// 测试模块
module test_costas_loop;
reg clk;
reg [1:0] i, q;
wire [31:0] freq_word;

costas_loop cl(.clk(clk), .i_in(i), .q_in(q), .freq_word(freq_word));

initial begin
clk = 0;
i = 2'd1;
q = 2'd0;

#10;

for (int i = 0; i < 100; i = i + 1) begin
i = ~i;
q = ~q;
#10;
end

$finish;
end

always #5 clk = ~clk;
endmodule