Verilog实现QPSK的costas环的模块，15位IQ信号进入鉴相器计算误差信号，再由环路滤波器输出dds的频率控制字

以下是一个实现QPSK的Costas环模块的Verilog代码示例。这个模块接受15位IQ信号，并计算误差信号，然后将误差信号输入环路滤波器，最后输出DDS的频率控制字。

module costas (
    input clk,
    input rst,
    input signed [14:0] i,
    input signed [14:0] q,
    output reg signed [31:0] ctrl_word
);

parameter F_REF = 10_000_000; // 参考频率
parameter F_CARRIER = 2_000_000; // 载波频率
parameter F_STEP = F_REF / (1 << 23); // DDS步进值

reg signed [14:0] i_reg;
reg signed [14:0] q_reg;
reg signed [14:0] i_delay;
reg signed [14:0] q_delay;
reg signed [14:0] i_err;
reg signed [14:0] q_err;
reg signed [31:0] ctrl_word_reg;
reg signed [31:0] ctrl_word_delay;

// 鉴相器
always @(posedge clk) begin
    if (rst) begin
        i_reg <= 0;
        q_reg <= 0;
        i_delay <= 0;
        q_delay <= 0;
        i_err <= 0;
        q_err <= 0;
        ctrl_word_reg <= 0;
        ctrl_word_delay <= 0;
    end else begin
        i_reg <= i;
        q_reg <= q;
        i_delay <= i_reg;
        q_delay <= q_reg;
        i_err <= q_delay - q_reg;
        q_err <= i_reg - i_delay;
    end
end

// 环路滤波器
always @(posedge clk) begin
    if (rst) begin
        ctrl_word_reg <= 0;
        ctrl_word_delay <= 0;
    end else begin
        ctrl_word_reg <= ctrl_word_delay + i_err * F_STEP;
        ctrl_word_delay <= ctrl_word_reg;
    end
end

assign ctrl_word = ctrl_word_reg;

endmodule