`timescale 1n/1ps module shiyan3( input clk, input rst, output seg_pi, output [7:0] seg_data ); reg[31:0]time_cnt; reg[7:0]num_cnt; always@(posedge clk or negedge rst) begin if(rst==1'b0) begin time_cnt<=32'd0; end else if(time_cnt==32'd49_000_000) begin time_cnt<=0; if(num_cnt==8'd10) begin num_cnt<=0; end else begin num_cnt<=num_cnt+1; end end else begin time_cnt<=time_cnt+32'd1; end end reg[7:0] seg_get_data; always@(posedge clk) begin if(num_cnt==8'd0) begin seg_get_data<=8'b1100_0000; end else if(num_cnt==8'd1) begin seg_get_data<=8'b1111_1001; end else if(num_cnt==8'd2) begin seg_get_data<=8'b1010_0100; end else if(num_cnt==8'd3) begin seg_get_data<=8'b1011_0000; end else if(num_cnt==8'd4) begin seg_get_data<=8'b1001_1001; end else if(num_cnt==8'd5) begin seg_get_data<=8'b1001_0010; end else if(num_cnt==8'd6) begin seg_get_data<=8'b1000_0010; end else if(num_cnt==8'd7) begin seg_get_data<=8'b1111_1000; end else if(num_cnt==8'd8) begin seg_get_data<=8'b1000_0000; end else if(num_cnt==8'd9) begin seg_get_data<=8'b1001_0000; end end assign seg_data=seg_get_data; endmodule 上述代码只能实现一位十进制的数字时钟，参考以上代码要求根据cyclone IV E 的FPGA实验板功能，设计四位数码管显示的数字时钟；要求：数字时钟能够准确计时并显示；开机显示00；具备控制功能按键有3个：清零、暂停、计时开始。数码管片四个选接口：DIG1，DIG2，DIG3，DIG4，数码管八个段选接口：SEG0，SEG1，SEG2，SEG3，SEG4，SEG5，SEG6，SEG7，给出Verilog代码

以下是四位数码管显示的数字时钟的Verilog代码，包含清零、暂停和计时开始功能：

module digital_clock(
    input clk,
    input rst,
    input btn_clear,
    input btn_pause,
    input btn_start,
    output [6:0] seg,
    output [3:0] dig
);

  reg [31:0] cnt;
  reg [3:0] num [0:9];

  reg [1:0] dig_sel;
  reg [6:0] seg_out;

  assign seg = seg_out;
  assign dig = {~dig_sel[3], ~dig_sel[2], ~dig_sel[1], ~dig_sel[0]};

  initial begin
    cnt <= 0;
    num[0] <= 7'b110_0000;
    num[1] <= 7'b111_1001;
    num[2] <= 7'b101_0100;
    num[3] <= 7'b101_1000;
    num[4] <= 7'b100_1101;
    num[5] <= 7'b100_1010;
    num[6] <= 7'b100_0010;
    num[7] <= 7'b111_1000;
    num[8] <= 7'b100_0000;
    num[9] <= 7'b100_1000;
  end

  always @(posedge clk or negedge rst) begin
    if (~rst) begin
      cnt <= 0;
      dig_sel <= 2'b00;
      seg_out <= num[0];
    end else if (btn_clear) begin
      cnt <= 0;
      dig_sel <= 2'b00;
      seg_out <= num[0];
    end else if (btn_pause) begin
      dig_sel <= 2'b11;
    end else if (btn_start) begin
      dig_sel <= 2'b00;
      if (cnt == 50000000) begin
        cnt <= 0;
        if (dig_sel == 2'b11) begin
          seg_out <= seg_out;
        end else begin
          seg_out <= num[cnt % 100 / 10] << 1;
          case (dig_sel)
            2'b00: seg_out <= seg_out | 1'b0;
            2'b01: seg_out <= seg_out | 1'b1;
            2'b10: seg_out <= seg_out | 1'bx;
          endcase
          dig_sel <= dig_sel + 1;
        end
      end else begin
        cnt <= cnt + 1;
      end
    end
  end

endmodule

模块接口说明：

- `clk`：时钟信号
- `rst`：复位信号，低电平有效
- `btn_clear`：清零按键信号，按下为高电平
- `btn_pause`：暂停按键信号，按下为高电平
- `btn_start`：开始计时按键信号，按下为高电平
- `seg`：数码管段选信号，输出七段数码管的亮灭状态
- `dig`：数码管位选信号，输出数码管的位选状态

模块功能说明：

- 数字计时器可以准确计时并显示
- 开机显示00
- 按下清零按键时，计时器清零并显示00
- 按下暂停按键时，数字时钟停止计时，但不清零
- 按下计时开始按键时，数字时钟开始计时并显示计时结果
- 数码管的四个位选信号分别为DIG1、DIG2、DIG3、DIG4
- 数码管的八个段选信号分别为SEG0、SEG1、SEG2、SEG3、SEG4、SEG5、SEG6、SEG7