FPGA设计：（1）拨动开关sw1为H，开始比赛。八位七数码管从左数第1、2位显示黄队分数，第7、8位显示红队分数。开始比赛时同时显示为00。按下键盘1代表黄队加1分；按下键盘2代表黄队加2分；按下键盘*3代表黄队加3分；同时对应的黄色led灯亮。按下键盘#1代表红队加1分；按下键盘#2代表红队加2分；按下键盘#3代表红队加3分；同时对应的红色led灯亮。 （2）拨动开关sw1为L，结束比赛。总分大的队伍对应颜色的led灯闪烁（闪烁频率为4Hz）， （3）外部输入脉冲信号频率为50mhz；给出各模块代码

以下是一个简单的FPGA设计代码，用于实现您描述的数电实验篮球比赛记分牌功能：

顶层模块：

module basketball_scoreboard(
    input clk,
    input rst,
    input sw,
    input btn1,
    input btn2,
    input btn3,
    output reg [7:0] seg,
    output reg [7:0] an,
    output reg led_yellow,
    output reg led_red
);

reg [3:0] yellow_score;
reg [3:0] red_score;
reg [1:0] blink_count;
reg [1:0] blink_rate;

parameter BLINK_RATE = 2;

assign led_yellow = (blink_rate == BLINK_RATE && yellow_score > red_score);
assign led_red = (blink_rate == BLINK_RATE && red_score > yellow_score);

seven_segment_display sseg(.seg(seg), .an(an), .data({yellow_score, yellow_score, 0, 0, 0, 0, red_score, red_score}));

always @(posedge clk) begin
    if (rst) begin
        yellow_score <= 0;
        red_score <= 0;
        blink_count <= 0;
        blink_rate <= 0;
    end else if (sw) begin
        case ({btn3, btn2, btn1})
            3'b001: yellow_score <= yellow_score + 1;
            3'b010: yellow_score <= yellow_score + 2;
            3'b011: yellow_score <= yellow_score + 3;
            3'b100: red_score <= red_score + 1;
            3'b101: red_score <= red_score + 2;
            3'b110: red_score <= red_score + 3;
            default:;
        endcase
    end else begin
        if (yellow_score > red_score) begin
            led_yellow <= ~led_yellow;
            blink_count <= blink_count + 1;
            if (blink_count == 4) begin
                blink_rate <= blink_rate + 1;
                blink_count <= 0;
            end
        end else if (red_score > yellow_score) begin
            led_red <= ~led_red;
            blink_count <= blink_count + 1;
            if (blink_count == 4) begin
                blink_rate <= blink_rate + 1;
                blink_count <= 0;
            end
        end
    end
end

endmodule

七段数码管显示模块：

module seven_segment_display(
    input [7:0] data,
    input [7:0] an,
    output reg [6:0] seg
);

reg [31:0] counter;

parameter CLK_FREQ = 50000000;
parameter DISPLAY_FREQ = 1000;

always @(posedge clk) begin
    counter <= counter + 1;
    if (counter == CLK_FREQ / DISPLAY_FREQ) begin
        counter <= 0;
    end
end

always @(posedge clk) begin
    case (an)
        8'h7F: seg <= 7'b0111111;
        8'hBF: seg <= 7'b0000110;
        8'hDF: seg <= 7'b1011011;
        8'hEF: seg <= 7'b1001111;
        8'hF7: seg <= 7'b1100110;
        8'hFB: seg <= 7'b1101101;
        8'hFD: seg <= 7'b1111101;
        8'hFE: seg <= 7'b0000111;
        default:;
    endcase
end

assign seg = (counter < CLK_FREQ / DISPLAY_FREQ / 2) ? data[6:0] : 7'b1111111;

endmodule

需要注意的是，这个设计代码只是一个简单的示例，具体实现还需要结合FPGA芯片型号和开发板型号进行相应的修改。同时，需要进行仿真和测试，以确保设计的正确性和可靠性。