verilog写一个FIFO的代码

下面是一个简单的Verilog代码实现FIFO:

module fifo (input clk, rst, wr_en, rd_en,
             input [7:0] wr_data,
             output reg [7:0] rd_data,
             output reg full,
             output reg empty);

  reg [7:0] mem [0:7];
  reg [2:0] head, tail;
  
  always @(posedge clk) begin
    if (rst) begin
      head <= 0;
      tail <= 0;
      rd_data <= 0;
      full <= 0;
      empty <= 1;
    end
    else begin
      if (wr_en && !full) begin
        mem[head] <= wr_data;
        head <= head + 1;
        if (head == 8) head <= 0;
        if (head == tail) full <= 1;
        empty <= 0;
      end
      if (rd_en && !empty) begin
        rd_data <= mem[tail];
        tail <= tail + 1;
        if (tail == 8) tail <= 0;
        if (tail == head) empty <= 1;
        full <= 0;
      end
    end
  end
endmodule

该FIFO模块包括8个字节的存储器，头指针和尾指针。当写入使能信号wr_en高电平时，数据被写入存储器。当读取使能信号rd_en高电平时，数据从存储器中读出。FIFO满时，full高电平，空时，empty高电平。当rst信号高电平时，FIFO被清零。