module gpr(a,b,clock,reg_write,num_write,rs,rt,data_write); output reg[31:0] a; output reg[31:0] b; input clock; input reg_write; input [4:0] rs; //读寄存器1 input [4:0] rt; //读寄存器2 input [4:0] num_write; //写寄存器 input [31:0] data_write; //写数据 reg [31:0] gp_registers[31:0]; //32个寄存器 always @(posedge clock) begin if(reg_write) begin gp_registers[num_write] <= data_write; end else begin a <= gp_registers[rs]; b <= gp_registers[rt]; end end endmodule

这是一个修正后的版本，包括了 a 和 b 输出信号的修正和使用 reg 修饰输出信号：

module gpr(a, b, clock, reg_write, num_write, rs, rt, data_write);
    output reg [31:0] a;
    output reg [31:0] b;
    input clock;
    input reg_write;
    input [4:0] rs; //读寄存器1
    input [4:0] rt; //读寄存器2
    input [4:0] num_write; //写寄存器
    input [31:0] data_write; //写数据
    reg [31:0] gp_registers[31:0]; //32个寄存器

    always @(posedge clock) begin
        if(reg_write) begin
            gp_registers[num_write] <= data_write;
        end else begin
            a <= gp_registers[rs];
            b <= gp_registers[rt];
        end
    end
endmodule