运用verilog语言编写一个由4个6输入LUT构成的128位移位寄存器
时间: 2024-06-06 13:11:06 浏览: 14
module shift_register(input clk, input reset, input shift, input [5:0] data_in, output [127:0] data_out);
reg [127:0] reg;
wire [5:0] lut_out0, lut_out1, lut_out2, lut_out3;
assign lut_out0 = {reg[5:0], data_in};
assign lut_out1 = {reg[13:8], data_in};
assign lut_out2 = {reg[21:16], data_in};
assign lut_out3 = {reg[29:24], data_in};
lut6 #(.LUT_INIT(128'h5555555555555555)) lut0(.I0(shift), .I1(lut_out0[0]), .I2(lut_out0[1]), .I3(lut_out0[2]), .I4(lut_out0[3]), .I5(lut_out0[4]), .O(lut_out0[5]));
lut6 #(.LUT_INIT(128'h5555555555555555)) lut1(.I0(lut_out0[5]), .I1(lut_out1[0]), .I2(lut_out1[1]), .I3(lut_out1[2]), .I4(lut_out1[3]), .I5(lut_out1[4]), .O(lut_out1[5]));
lut6 #(.LUT_INIT(128'h5555555555555555)) lut2(.I0(lut_out1[5]), .I1(lut_out2[0]), .I2(lut_out2[1]), .I3(lut_out2[2]), .I4(lut_out2[3]), .I5(lut_out2[4]), .O(lut_out2[5]));
lut6 #(.LUT_INIT(128'h5555555555555555)) lut3(.I0(lut_out2[5]), .I1(lut_out3[0]), .I2(lut_out3[1]), .I3(lut_out3[2]), .I4(lut_out3[3]), .I5(lut_out3[4]), .O(lut_out3[5]));
always @(posedge clk) begin
if (reset) begin
reg <= 0;
end else if (shift) begin
reg <= {lut_out3, reg[127:30]};
end else begin
reg <= {lut_out3, lut_out2, lut_out1, lut_out0};
end
end
assign data_out = reg;
endmodule
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