用case实现round robin 5路verilog实现 与tb文件

以下是Round Robin 5路Verilog的代码实现：

module round_robin_5(input clk, input rst, input [4:0] req, output reg [4:0] grant);

reg [2:0] cnt;

always @ (posedge clk or posedge rst) begin
    if (rst) begin
        cnt <= 3'b0;
        grant <= 5'b0;
    end
    else begin
        cnt <= cnt + 1;
        if (cnt == 3'b100) begin
            cnt <= 3'b0;
        end
    end
end

always @ (posedge clk or posedge rst) begin
    if (rst) begin
        grant <= 5'b0;
    end
    else begin
        case (cnt)
            3'b000: grant <= req[0] ? 5'b00001 : grant;
            3'b001: grant <= req[1] ? 5'b00010 : grant;
            3'b010: grant <= req[2] ? 5'b00100 : grant;
            3'b011: grant <= req[3] ? 5'b01000 : grant;
            3'b100: grant <= req[4] ? 5'b10000 : grant;
        endcase
    end
end

endmodule

以下是对应的testbench文件：

module round_robin_5_tb;

reg clk;
reg rst;
reg [4:0] req;
wire [4:0] grant;

round_robin_5 dut (.clk(clk), .rst(rst), .req(req), .grant(grant));

initial begin
    clk = 0;
    rst = 1;
    req = 5'b0;
    #10 rst = 0;
    #10 req = 5'b00001;
    #10 req = 5'b00010;
    #10 req = 5'b00100;
    #10 req = 5'b01000;
    #10 req = 5'b10000;
    #10 $finish;
end

always #5 clk = ~clk;

endmodule

在testbench文件中，我们使用了一个时钟以及一个复位信号。我们在第10个时钟周期后取消了复位信号，并在随后的每个时钟周期设置了一个请求信号。您可以根据您的实际需要更改这些操作。