uvm sequence启动
时间: 2023-09-09 17:12:19 浏览: 132
在uvm中,sequence的启动有两种方式:default_sequence启动方式和非default_sequence启动方式。
1. default_sequence启动方式:这种方式是最常用的启动sequence的方法,它会隐式地调用start函数来启动sequence。在sequencer的main_phase中,可以使用以下代码启动sequence:
```verilog
task my_sequencer::main_phase(phase);
seq.starting_phase = phase;
seq.start(this);
endtask
```
在sequence的body函数中,可以使用以下代码控制仿真时间并启动sequence:
```verilog
task my_sequence::body();
if(starting_phase != null) starting_phase.raise_objection(this);
// 执行sequence的内容
if(starting_phase != null) starting_phase.drop_objection(this);
endtask
```
2. 非default_sequence启动方式:在不使用default_sequence启动方式时,可以通过uvm_config_db来配置并启动sequence。以下是一个示例代码:
```verilog
uvm_config_db#(uvm_object_wrapper)::set(this,"env.i_agt.sqr.main_phase","default_sequence",my_sequence::type_id::get());
```
上述代码将my_sequence作为default_sequence配置到env.i_agt.sqr.main_phase中,并在main_phase中启动该sequence。
总结起来,uvm sequence的启动方式可以通过default_sequence启动方式或者非default_sequence启动方式来实现。在具体的代码中,可以根据需要调用start函数或者使用uvm_config_db来配置并启动sequence。<span class="em">1</span><span class="em">2</span><span class="em">3</span>
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