镁光HMC Gen2 160GB/s DRAM：高带宽封装与特性概览

DRAM

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Table 5: Scrambler Logic Seed Values

Lane Seed Value Lane Seed Value

0 15'h4D56 8 15'h3EB3

1 15'h47FF 9 15'h2769

2 15'h75B8 10 15'h4580

3 15'h1E18 11 15'h5665

4 15'h2E10 12 15'h6318

5 15'h3EB2 13 15'h6014

6 15'h4302 14 15'h077B

7 15'h1380 15 15'h261F

Note:

1. Scrambler logic seed values for lanes 0–7 are the same with full-width and half-width

configurations.

Table 6 contains a series of NULL packets to illustrate how the scrambler operates on

each lane. The Lane 0 LFSR starts with seed value 0xCD56. This is the 15-bit seed value

from Table 5 (15'h4D56) with the next (16th) bit of the PRBS included to enable scram-

bling of 16 data payload bits per clock cycle; the scrambler PRBS is calculated at 16 bits

per clock cycle. The scrambler LFSR[15:0] is bitwise exclusive-OR'ed with data[15:0] to

generate scrambled data. When NULLs, or all zeroes payload data per lane, are scram-

bled, the continual exclusive-or with (payload) zero causes the scrambled data to be

identical to the scrambler LFSR value each clock cycle. As a result, the list of the scram-

bler LFSR sequence is also the list of scrambled data when the payload data is all

NULLs.

Hybrid Memory Cube – HMC Gen2

Logical Sub-Block of Physical Layer

09005aef8462cb46

hmc_gen2.pdf - Rev. H 2/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 7: TS1 Definition

TS1 Bit Position

(Sent

Last)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1

(Sent

First)

1 1 1 1 0 0 0 0 L L L L S S S S

0xF 0x0 Dependant on lane

Sequence

Notes:

1. Lane field = 0xC for lane 15, or lane 7 in half-width configuration, 0x3 for lane 0, and

0x5 for all other lanes.

2. Sequence[3:0] is a 4-bit counter that increments from 0 to 15 with each successive TS1

sent on a lane. The sequence value will roll back to 0 after 15 is reached.

3. The half-width link configuration uses lanes 0–7.

4. The 2-byte TS1 character establishes the framing that identifies byte pairs that belong to

the same FLIT after training completes in half-width mode. The transition from sending

TS1s to sending NULL FLITs can occur on any byte boundary within the entire 32-byte

TS1 sequence, including mid-TS1 character, so this transition boundary to NULL bytes

should NOT be used to infer the FLIT boundary in half-width configuration.

Table 8: TS1 Training Sequence Example

TS1 Ordering Lane 0 Lane 1–14 Lane 15

0 16'hF030 16'hF050 16'hF0C0

1 16'hF031 16'hF051 16'hF0C1

2 16'hF032 16'hF052 16'hF0C2

3 16'hF033 16'hF053 16'hF0C3

... ... ... ...

14 16'hF03E 16'hF05E 16'hF0CE

15 16'hF03F 16'hF05F 16'hF0CF

Lane Run Length Limitation

For each HMC RX lane, the scrambled data pattern must meet a run length limit of 85

UI. This is the maximum number of consecutive identical digits allowed. A run of 86 or

more consecutive ones (or zeroes) must not be generated by the transmitter on any of

the downstream lanes at any time. This restriction is in place so that the clock recovery

circuit at each HMC RX lane meets its minimum required transition density to assure

correct data alignment. This restriction does not require a particular implementation of

the transmitter logic, as long as the run length limit is met at HMC RX lane inputs.

Although a given host may not have a run length limit on the scrambled upstream data,

HMC is designed to meet run length limitations of 85 UI on each lane at all times. This

is implemented through HMC’s ability to monitor the scrambled data at each TX lane. If

the scrambled TX data on any lane exceeds 85 consecutive digits, the TX scramble logic

forces at least one transition. Forcing a transition corrupts the upstream response and

results in a link retry (see Link Retry). The probability of such an event is approximately

-80

for random payload data. HMC's run length limitation feature may be disabled

within the mode register.

Hybrid Memory Cube – HMC Gen2

Logical Sub-Block of Physical Layer

09005aef8462cb46

hmc_gen2.pdf - Rev. H 2/18 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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