2022年RFIC专题：5G与毫米波技术的创新应用

JSSC

需积分: 9 55 浏览量更新于2024-06-28 收藏 133.64MB PDF 举报

身份认证购VIP最低享 7 折!

领优惠券(最高得80元）

"JSSC 2022.05 特别专题：2021年RFIC研讨会" 这篇摘要提及的是《国际固态电路学会期刊》(IJSCBC) 2022年5月刊(Volume 57, Number 5)，特别专题聚焦于2021年的RFIC（射频集成电路）研讨会。这个研讨会是射频技术领域的顶级会议，聚集了全球的研究者和工程师，展示和讨论最新的射频集成电路设计和应用。嘉宾编辑导言由D.M.W. Leenaerts撰写，介绍了这个特别专题的内容和意义。该专题包含了多篇论文，这些论文详细阐述了不同领域的创新技术，主要集中在射频和毫米波（mmWave）技术在5G通信中的应用。第一篇论文"A 25–34-GHz Eight-Element MIMO Transmitter for Keyless High Throughput Directionally Secure Communication"由N.S. Mannem等人贡献，介绍了一种25到34 GHz频段的八元素MIMO（多输入多输出）发射机，旨在实现无钥匙高通量、方向性安全通信。MIMO技术通过使用多个天线同时传输数据，显著提高了无线通信系统的容量和安全性。第二篇论文"A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP Control"由V. Bhagavatula等人提出，他们设计了一个5G FR2（频率范围2）功率放大器，集成了功率检测器，用于闭环EIRP（等效全向辐射功率）控制。这种集成解决方案有助于优化5G基站的功率输出和效率。第三篇论文"Single Transformer-Based Compact Doherty Power Amplifiers for 5G RF Phased-Array ICs"由H.-C. Park等人展示了单变压器紧凑型Doherty功率放大器在5G射频相控阵集成电路中的应用，这种设计可以减小尺寸并提高效率。第四篇论文"AMulti-Band 16–52-GHz Transmit Phased Array Employing 4×1 Beamforming IC With 14–15.4-dBm Psat for 5G NR FR2 Operation"由A. Alhamed等人报告，他们开发了一个多频段16到52 GHz的发射相位阵列，采用4×1波束成形集成电路，适用于5G NR FR2操作，具有14到15.4 dBm的饱和功率输出，这在5G网络中对于提供广泛的覆盖和高速数据传输至关重要。第五篇论文"High-Efficiency Class-E Power Amplifiers for mmWave Radar Sensors: Design and Implementation"由T. Dinc等人讨论了用于毫米波雷达传感器的高效率Class-E功率放大器的设计与实现，这类放大器在毫米波雷达系统中用于提高探测精度和能效。最后，还提到了一篇关于140GHz频率范围内射频集成电路的文章，但具体内容没有给出。这些论文共同揭示了射频集成电路在5G通信、毫米波雷达传感器以及高效功率放大器等领域的最新进展，反映了当前科研工作的热点和挑战。

资源详情

资源推荐

1254 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 5, MAY 2022

TABLE II

HASE AND AMPLITUDE IQ IMBALANCE REQUIREMENTS FOR TWO-WAY CDA TX

Fig. 16. Simulated constellations for two-way CDA TX with the receiving

eavesdropper at 5

◦

against leakages (−5, −10 dB, no leakage).

Fig. 17. Simulated rms EVM (%) versus scan angle for a two-way

CDA TX with TX element-to-element coupling with leakage levels from

−30 to −5 dB at a 5-dB step and no leakage.

and QPSK, the imbalance requirement is a bit more stringent

than the symmetric case since the mismatches add up.

D. Effect of Coupling Between Channels on Security

In this section, we quantitatively analyze the effects of

signal leakage (coupling) between TXs. We considered a

simple case of two-channel CDA TX, i.e., 16QAM

+ QPSK

Due to leakage between channels, i.e., from 16QAM TX to

QPSK4 TX and vice versa, the security performance of the

overall system could be affected. As shown in Fig. 16, the

EVM of 64QAM constellations observed at eavesdropper (5

◦

)

due to leakage reduces from 13.2% at no leakage to 3.6%

at −5 dB leakage. Fig. 17 shows the EVM performance

versus scan angle over different amounts of leakage. With

an ideal simulation test bench, even with a −20-dB leakage

between TXs, the IB of the proposed scheme only degrades

to ∼14

◦

against 10

◦

for the case with no leakage. Here, the

IB is deﬁned for a worst case EVM of 12%. We performed

simulations up to extreme leakages of −5dB,wheretheIB

increases to only 30

◦

(±15

◦

). Please note that the simulations

are performed only for the CDA scheme without temporal

swapping for the sake of brevity, but degradation could also

be expected for the case of temporal swapping CDA.

CKNOWLEDGMENT

The authors would like to thank GlobalFoundries for

providing multi project wafer (MPW) tapeout opportunities

and the members of Georgia Tech Electronics and Micro-

System (GEMS) Group, Georgia Tech, for valuable technical

discussions.

EFERENCES

[1] M. Bloch and J. Barros, Physical-Layer Security: From Information

Theory to Security Engineering. Cambridge, U.K.: Cambridge Univ.

Press, 2011.

[2] M. Bloch, J. Barros, M. R. D. Rodrigues, and S. W. McLaughlin, “Wire-

less information-theoretic security,” IEEE Trans. Inf. Theory, vol. 54,

no. 6, pp. 2515–2534, Jun. 2008.

[3] Y. Liu, H.-H. Chen, and L. Wang, “Physical layer security for next gen-

eration wireless networks: Theories, technologies, and challenges,” IEEE

Commun. Surveys Tuts., vol. 19, no. 1, pp. 347–376, 1st Quart., 2017.

[4] J. M. Hamamreh, H. M. Furqan, and H. Arslan, “Classiﬁcations and

applications of physical layer security techniques for conﬁdentiality: A

comprehensive survey,” IEEE Commun. Surveys Tuts., vol. 21, no. 2,

pp. 1773–1828, 2nd Quart., 2019.

[5] Y.-S. Shiu, S. Y. Chang, H.-C. Wu, S. C.-H. Huang, and H.-H. Chen,

“Physical layer security in wireless networks: A tutorial,” IEEE Wireless

Commun., vol. 18, no. 2, pp. 66–74, Apr. 2011.

[6] A. Babakhani, D. B. Rutledge, and A. Hajimiri, “A near-ﬁeld mod-

ulation technique using antenna reﬂector switching,” in IEEE Int.

Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2008,

pp. 188–605.

[7] J. Chen et al., “A digitally modulated mm-wave Cartesian beamforming

transmitter with quadrature spatial combining,” in IEEE Int. Solid-State

Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2013, pp. 232–233.

[8] J. Guo, L. Poli, M. A. Hannan, P. Rocca, S. Yang, and A. Massa,

“Time-modulated arrays for physical layer secure communications:

Optimization-based synthesis and experimental assessment,” IEEE

Trans. Antennas Propag., vol. 66, no. 12, pp. 6939–6949, Dec. 2018.

[9] X. Lu, S. Venkatesh, B. Tang, and K. Sengupta, “4.6 space-time

modulated 71-to-76 GHz mm-wave transmitter array for physically

secure directional wireless links,” in IEEE Int. Solid-State Circuits Conf.

(ISSCC) Dig. Tech. Papers, Feb. 2020, pp. 86–88.

[10] Q. Zhu, S. Yang, R. Yao, and Z. Nie, “Directional modulation based

on 4-D antenna arrays,” IEEE Trans. Antennas Propag., vol. 62, no. 2,

pp. 621–628, Feb. 2014.

[11] C. Liang and B. Razavi, “Transmitter linearization by beamforming,”

IEEE J. Solid-State Circuits, vol. 46, no. 9, pp. 1956–1969, Sep. 2011.

[12] H. Wang, H. Mohammadnezhad, and P. Heydari, “Analysis and design

of high-order QAM direct-modulation transmitter for high-speed point-

to-point mm-wave wireless links,” IEEE J. Solid-State Circuits, vol. 54,

no. 11, pp. 3161–3179, Nov. 2019.

MANNEM et al.: 25–34-GHz EIGHT-ELEMENT MIMO TX 1255

[13] N. S. Mannem, T.-Y. Huang, E. Erfani, S. Li, and H. Wang, “A mm-

wave transmitter MIMO with constellation decomposition array (CDA)

for keyless physically secured high-throughput links,” in Proc. IEEE

Radio F req. Integr. Circuits Symp. (RFIC), Jun. 2021, pp. 199–202.

[14] S. Shakib, M. Elkholy, J. Dunworth, V. Aparin, and K. Entesari,

“A wideband 28 GHz power ampliﬁer supporting 8×100 MHz carrier

aggregation for 5G in 40 nm CMOS,” in IEEE Int. Solid-State Circuits

Conf. (ISSCC) Dig. Tech. Papers, Feb. 2017, pp. 44–45.

[15] M. Bellare, S. Tessaro, and A. Vardy, “Semantic security for the wiretap

channel,” in Proc. Annu. Cryptol. Conf. Berlin, Germany: Springer-

Verlag, 2012, pp. 294–311.

[16] A. D. Wyner, “The wire-tap channel,” Bell Syst. Tech. J ., vol. 54, no. 8,

pp. 1355–1387, Jan. 1975.

[17] I. Csiszár and J. Korner, “Broadcast channels with conﬁdential mes-

sages,” IEEE Trans. Inf. Theory, vol. IT-24, no. 3, pp. 339–348,

May 1978.

[18] M. Bloch, M. Hayashi, and A. Thangaraj, “Error-control coding for

physical-layer secrecy,” Proc. IEEE, vol. 103, no. 10, pp. 1725–1746,

Oct. 2015.

[19] S. Y. Kim, O. Inac, C. Kim, D. Shin, and G. M. Rebeiz, “A 76–84-GHz

16-element phased-array receiver with a chip-level built-in self-test sys-

tem,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 8, pp. 3083–3098,

Aug. 2013.

[20] M.-Y. Huang, T. Chi, F. Wang, and H. Wang, “An all-passive negative

feedback network for broadband and wide ﬁeld-of-view self-steering

beam-forming with zero DC power consumption,” IEEE J. Solid-State

Circuits, vol. 52, no. 5, pp. 1260–1273, May 2017.

[21] N. N. Alotaibi and K. A. Hamdi, “Switched phased-array transmission

architecture for secure millimeter-wave wireless communication,” IEEE

Trans. Commun., vol. 64, no. 3, pp. 1303–1312, Mar. 2016.

[22] S. Venkatesh, X. Lu, and K. Sengupta, “Spatio-temporal modulated mm-

wave arrays for physical layer security and resiliency against distributed

eavesdropper attacks,” in Proc. 5th ACM Workshop Millim.-Wave THz

Netw. Sens. Syst., Oct. 2021, pp. 19–24.

[23] D. Munzer, N. S. Mannem, and H. Wang, “A single-ended coupler-based

VSWR resilient joint mm-wave true power detector and impedance sen-

sor,” IEEE Microw. Wireless Compon. Lett., vol. 31, no. 6, pp. 812–815,

Jun. 2021.

[24] S. Jeon et al., “A scalable 6-to-18 GHz concurrent dual-band quad-beam

phased-array receiver in CMOS,” IEEE J. Solid-State Circuits, vol. 43,

no. 12, pp. 2660–2673, Dec. 2008.

[25] N. S. Mannem, M.-Y. Huang, T.-Y. Huang, and H. Wang, “A recon-

ﬁgurable hybrid series/parallel Doherty power ampliﬁer with antenna

VSWR resilient performance for MIMO arrays,” IEEE J. Solid-State

Circuits, vol. 55, no. 12, pp. 3335–3348, Dec. 2020.

[26] K.-J. Koh, J. W. May, and G. M. Rebeiz, “A millimeter-wave

(40–45 GHz) 16-element phased-array transmitter in 0.18-μmSiGe

BiCMOS technology,” IEEE J. Solid-State Circuits, vol. 44, no. 5,

pp. 1498–1509, May 2009.

[27] K. Kibaroglu, M. Sayginer, and G. M. Rebeiz, “A low-cost scalable 32-

element 28-GHz phased array transceiver for 5G communication links

basedona2× 2 beamformer ﬂip-chip unit cell,” IEEE J. Solid-State

Circuits, vol. 53, no. 5, pp. 1260–1274, May 2018.

[28] A. Hajimiri, H. Hashemi, A. Natarajan, X. Guan, and A. Komijani,

“Integrated phased array systems in silicon,” Proc. IEEE, vol. 93, no. 9,

pp. 1637–1655, Sep. 2005.

[29] S. Shahramian, M. J. Holyoak, A. Singh, and Y. Baeyens, “A fully

integrated 384-element, 16-tile, W-band phased array with self-

alignment and self-test,” IEEE J. Solid-State Circuits, vol. 54, no. 9,

pp. 2419–2434, Sep. 2019.

[30] A. Valdes-Garcia et al., “A fully integrated 16-element phased-array

transmitter in SiGe BiCMOS for 60-GHz communications,” IEEE J.

Solid-State Circuits, vol. 45, no. 12, pp. 2757–2773, Dec. 2010.

[31] M.P.Daly,E.L.Daly,andJ.T.Bernhard, “Demonstration of directional

modulation using a phased array,” IEEE Trans. Antennas Propag.,

vol. 58, no. 5, pp. 1545–1550, May 2010.

[32] N. S. Mannem, T.-Y. Huang, and H. Wang, “Broadband active load-

modulation power ampliﬁcation using coupled-line baluns: A multifre-

quency role-exchange coupler Doherty ampliﬁer architecture,” IEEE J.

Solid-State Circuits, vol. 56, no. 10, pp. 3109–3122, Oct. 2021.

[33] N. Valliappan, A. Lozano, and R. W. Heath, Jr., “Antenna subset

modulation for secure millimeter-wave wireless communication,” IEEE

Trans. Commun., vol. 61, no. 8, pp. 3231–3245, Aug. 2013.

[34] C. R. Chappidi, X. Lu, X. Wu, and K. Sengupta, “Antenna preprocessing

and element-pattern shaping for multi-band mmWave arrays: Multi-port

transmitters and antennas,” IEEE J. Solid-State Circuits, vol. 55, no. 6,

pp. 1441–1454, Jun. 2020.

[35] A. Townley et al., “A 94-GHz 4TX–4RX phased-array FMCW radar

transceiver with antenna-in-package,” IEEE J. Solid-State Circuits,

vol. 52, no. 5, pp. 1245–1259, May 2017.

[36] A. Natarajan, A. Komijani, X. Guan, A. Babakhani, and A. Hajimiri,

“A 77-GHz phased-array transceiver with on-chip antennas in silicon:

Transmitter and local LO-path phase shifting,” IEEE J. Solid-State

Circuits, vol. 41, no. 12, pp. 2807–2819, Dec. 2006.

[37] A. Babakhani, G. Xiang, A. Komijani, A. Natarajan, and A. Hajimiri,

“A 77-GHz phased-array transceiver with on-chip antennas in silicon:

Receiver and antennas,” IEEE J. Solid-State Circuits, vol. 41, no. 12,

pp. 2795–2806, Dec. 2006.

[38] S. Shahramian, Y. Baeyens, N. Kaneda, and Y.-K. Chen,

“A 70–100 GHz direct-conversion transmitter and receiver phased

array chipset demonstrating 10 Gb/s wireless link,” IEEE J. Solid-State

Circuits, vol. 48, no. 5, pp. 1113–1125, May 2013.

[39] T. Sowlatiet et al., “A 60-GHz 144-element phased-array transceiver

for backhaul application,” IEEE J. Solid-State Circuits, vol. 53, no. 12,

pp. 3640–3659, Dec. 2018.

[40] B. Sadhu et al., “A 28-GHz 32-element TRX phased-array IC with

concurrent dual-polarized operation and orthogonal phase and gain

control for 5G communications,” IEEE J. Solid-State Circuits, vol. 52,

no. 12, pp. 3373–3391, Dec. 2017.

[41] S. Hu, F. Wang, and H. Wang, “A 28-/37-/39-GHz linear Doherty power

ampliﬁer in silicon for 5G applications,” IEEE J. Solid-State Circuits,

vol. 54, no. 6, pp. 1586–1599, Jun. 2019.

[42] T.-Y. Huang, N. S. Mannem, S. Li, D. Jung, M.-Y. Huang, and H. Wang,

“A 26-to-60 GHz continuous coupler-Doherty linear power ampliﬁer for

over-an-octave back-off efﬁciency enhancement,” in IEEE Int. Solid-

State Circuits Conf. (ISSCC) Dig. Tech. Papers, vol. 64, Feb. 2021,

pp. 354–356.

[43] M.-Y. Huang, T. Chi, F. Wang, T.-W. Li, and H. Wang, “A 23-to-30 GHz

hybrid beamforming MIMO receiver array with closed-loop multistage

front-end beamformers for full-FoV dynamic and autonomous unknown

signal tracking and blocker rejection,” in IEEE Int. Solid-State Circuits

Conf. (ISSCC) Dig. Tech. Papers, Feb. 2018, pp. 68–70.

[44] T. Yu and G. M. Rebeiz, “A 22–24 GHz 4-element CMOS phased array

with on-chip coupling characterization,” IEEE J. Solid-State Circuits,

vol. 43, no. 9, pp. 2134–2143, Sep. 2008.

[45] M.-Y. Huang and H. Wang, “A 27-to-41 GHz MIMO receiver with

N-input-N-output using scalable cascadable autonomous array-based

high-order spatial ﬁlters for instinctual full-FoV multi-blocker/signal

management,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech.

Papers, Feb. 2019, pp. 346–348.

[46] E. Naviasky, L. Iotti, G. LaCaille, B. Nikolic, E. Alon, and A. Niknejad,

“A 71-to-86 GHz packaged 16-element by 16-beam multi-user beam-

forming integrated receiver in 28 nm CMOS,” in IEEE Int. Solid-State

Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2021, pp. 218–220.

[47] J. Park, S. Lee, D. Lee, and S. Hong, “A 28 GHz 20.3%-transmitter-

efﬁciency 1.5

◦

-phase-error beamforming front-end IC with embedded

switches and dual-vector variable-gain phase shifters,” in IEEE Int.

Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2019,

pp. 176–178.

[48] H.-C. Park et al., “A 39 GHz-band CMOS 16-channel phased-array

transceiver IC with a companion dual-stream IF transceiver IC for 5G

NR base-station applications,” in IEEE Int. Solid-State Circuits Conf.

(ISSCC) Dig. Tech. Papers, Feb. 2020, pp. 76–78.

Naga Sasikanth Mannem (Student Member, IEEE)

received the B.Tech. and M.Tech. degrees in elec-

tronics and electrical communication engineering

with a specialization in very large-scale inte-

gration (VLSI) from IIT Kharagpur (IIT KGP),

Kharagpur, India, in 2018. He is currently pur-

suing the Ph.D. degree in electrical engineering

with the Georgia Institute of Technology, Atlanta,

GA, USA.

His research interest includes RF/millimeter-wave

(mm-wave) integrated circuits and systems.

Mr. Mannem was a recipient of the Analog Devices Inc., Outstanding

Student Designer Award in 2021 and the Best Student Paper Award Second

Place at IEEE Radio Frequency Integrated Circuits (RFIC) conference 2021,

and a co-recipient of the International Microwave Symposium (IMS) Best

Student Paper Award Second Place at IMS 2021.

1256 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 5, MAY 2022

Tzu-Yuan Huang (Graduate Student Member,

IEEE) received the B.S. degree in electrical and

computer engineering from National Chiao Tung

University (NCTU), Hsinchu, Taiwan, in 2012,

and the M.S. degree from the Graduate Institute

of Communication Engineering, National Taiwan

University (NTU), Taipei, Taiwan, in 2015.

He is currently pursuing the Ph.D. degree in

electrical engineering with the Georgia Institute of

Technology, Atlanta, GA, USA.

His current research interest includes

RF/millimeter-wave (mm-wave) integrated circuits and systems.

Elham Erfani (Member, IEEE) received the Ph.D.

degree in telecommunication engineering from the

Institute National de la Recherche Scientiﬁque

(INRS), Montreal, QC, Canada, in 2019.

From September 2015 to February 2017, she

joined the Centre for Intelligent Antenna and Radio

Systems (CIARS), University of Waterloo, Waterloo,

ON, Canada, as a Visiting Researcher to work

on the theoretical analysis and fabrication of a

planar transmit-array antenna for millimeter-wave

(mm-wave) backhaul applications. She has been with

the Georgia Tech Electronics and Micro-System (GEMS) Research Group,

Georgia Institute of Technology, Atlanta, GA, USA, as a Post-Doctoral

Researcher, working on mm-wave antenna-in-package and antenna-on chip,

since 2019. Her research interests include mm-wave antennas, artiﬁcial

materials, mm-wave receivers to transceivers, phased arrays, and mm-wave

integrated circuits.

Dr. Erfani was awarded the Alexander Graham Bell, Natural Sciences

and Engineering Research Council (NSERC), the Postgraduate Scholarships-

Doctoral Program (NSERC), and Fonds de Recherche du Qubec Nature et

Technologies (FRQNT) during her Ph.D. She is also a recipient of the NSERC

Postdoctoral Fellowship Scholarship.

Sensen Li (Member, IEEE) received the B.Eng.

(Hons.) and B.A. degrees from Zhejiang University,

Hangzhou, China, in 2013, and the Ph.D. degree

from the Georgia Institute of Technology, Atlanta,

GA, USA, in 2020.

He is currently working with Samsung Research

America, Ridgeﬁeld Park, NJ, USA, as a Research

Engineer, developing next-generation communica-

tion systems. His research interests include RF,

millimeter-wave (mm-wave), and terahertz (THz)

integrated antenna, circuit, and system designs for

wireless communication, radar, and hyperspectral imaging applications.

Dr. Li was a recipient of the First-Class Scholarship for outstanding

undergraduate students (Top 5%) of Zhejiang University from 2010 to 2013,

the Best Student Paper Award (second place) at the 2018 IEEE Radio

Frequency Integrated Circuits Symposium (RFIC), the IEEE Antennas and

Propagation Society (AP-S) Doctoral Research Grant in 2018, the Analog

Devices, Inc., Outstanding Student Designer Award in 2018, and the IEEE

Microwave Theory and Techniques Society (MTT-S) Graduate Fellowship in

2019. He was also a co-recipient of multiple best paper awards, including

the IEEE Custom Integrated Circuits Conference (CICC) Best Paper Award

in 2019, the IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

Best Student Paper Award (second place) in 2021, and the IEEE International

Microwave Symposium (IMS) Best Student Paper Award (second place)

in 2021.

David Munzer (Student Member, IEEE) received

the B.S. degree in electrical and computer engineer-

ing from the University of Florida, Gainesville, FL,

USA, in 2016, and the M.Sc. degree in electrical and

computer engineering from the Georgia Institute of

Technology, Atlanta, GA, USA, in 2018, where he

is currently pursuing the Ph.D. degree in electrical

and computer engineering (ECE).

His research interests include RF/millimeter-wave

(mm-wave) integrated circuits/systems and VSWR

resilient sensors.

Mr. Munzer was a recipient of the National Defense Science and Engi-

neering Graduate (NDSEG) Fellowship in 2019 and the Analog Devices Inc.

Outstanding Student Designer Award in 2021.

Matthieu R. Bloch (Senior Member, IEEE)

received the Engineering degree from Supélec,

Gif-sur-Yvette, France, in 2003, the M.S. degree in

electrical engineering from the Georgia Institute of

Technology, Atlanta, GA, USA, in 2003, the Ph.D.

degree in engineering science from the Université

de Franche-Comté, Besançon, France, in 2006, and

the Ph.D. degree in electrical engineering from the

Georgia Institute of Technology, in 2008.

From 2008 to 2009, he was a Post-Doctoral

Research Associate with the University of Notre

Dame, South Bend, IN, USA. Since July 2009, he has been a Faculty Member

with the School of Electrical and Computer Engineering, and from 2009 to

2013, he was with Georgia Tech Lorraine, Atlanta, GA. He is a Professor

with the School of Electrical and Computer Engineering, Georgia Institute

of Technology. His research interests are in the areas of information theory,

error-control coding, wireless communications, and cryptography.

Dr. Bloch has served on the organizing committee of several international

conferences. He was a co-recipient of the IEEE Communications Society and

IEEE Information Theory Society 2011 Joint Paper Award and the coauthor

of the textbook Physical-Layer Security: From Information Theory to Security

Engineering (Cambridge University Press). He was the Chair of the Online

Committee of the IEEE Information Theory Society from 2011 to 2014.

He has been on the Board of Governors of the IEEE Information Theory

Society since 2016 and currently serves as the second Vice-President. He was

an Associate Editor for the IEEE T

RANSACTIONS ON INFORMATION THE-

ORY from 2016 to 2019. He has been an Associate Editor for the IEEE

RANSACTIONS ON INFORMATION FORENSICS AND SECURITY since 2019.

Hua Wang (Senior Member, IEEE) received the

M.S. and Ph.D. degrees in electrical engineer-

ing from the California Institute of Technology,

Pasadena, CA, USA, in 2007 and 2009, respectively.

He held the Demetrius T. Paris Professorship with

the School of Electrical and Computer Engineering,

Georgia Institute of Technology (Georgia Tech),

Atlanta, GA, USA, where he was the Founding

Director of the Georgia Tech Center of Circuits and

Systems (CCS) and the Director of the Georgia Tech

Electronics and Micro-System (GEMS) Laboratory.

He worked with Intel Corporation, Santa Clara, CA, USA, and Skyworks

Solutions, Irvine, CA, USA, from 2010 to 2011. He is a Full Professor and the

Chair of electronics with the Department of Information Technology and Elec-

trical Engineering (D-ITET), Swiss Federal Institute of Technology Zürich

(ETH Zürich), Zürich, Switzerland. He is the Director of the ETH Integrated

Devices, Electronics, and Systems (IDEAS) Group, Zürich. He is also jointly

afﬁliated with the School of Electrical and Computer Engineering (ECE),

Georgia Tech. He has authored or coauthored over 200 peer-reviewed journal

articles and conference papers. He is interested in innovating analog, mixed-

signal, RF, and millimeter-wave (mm-wave) integrated circuits and hybrid

systems for wireless communication, sensing, and bioelectronics applications.

Dr. Wang is a Technical Program Committee (TPC) Member for IEEE

International Solid-State Circuits Conference (ISSCC), Radio Frequency Inte-

grated Circuit (RFIC), Custom Integrated Circuits Conference (CICC), and

BiCMOS and Compound Semiconductor Integrated Circuits and Technology

Symposium (BCICTS) conferences and a Steering Committee Member for

IEEE RFIC and CICC. He was a recipient of the National Science Foundation

CAREER Award in 2015, the Georgia Tech ECE Outstanding Junior Faculty

Member Award in 2015, the Lockheed Dean’s Excellence in Teaching Award

in 2015, the Georgia Tech Sigma Xi Young Faculty Award in 2016, the IEEE

Microwave Theory and Techniques Society (MTT-S) Outstanding Young Engi-

neer Award in 2017, the DARPA Young Faculty Award in 2018, the DARPA

Director’s Fellowship Award in 2020 (the ﬁrst awardee in Georgia Tech’s

history), and the Qualcomm Faculty Award in 2020 and 2021, respectively.

His research group has won multiple academic awards and best paper awards,

including the IEEE RFIC Best Student Paper Awards (2014, 2016, 2018, and

2021), the IEEE CICC Outstanding Student Paper Awards (2015, 2018, and

2019), the 2016 IEEE Microwave Magazine Best Paper Award, and the IEEE

SENSORS Best Live Demo Award (second place in 2016), the IEEE CICC

Best Conference Paper Award (2017), the 2019 Marconi Society Paul Baran

Young Scholar, and the IEEE International Microwave Symposium (IMS) Best

Student Paper Award 2021. He is the Conference Chair for CICC 2019 and

Conference General Chair for CICC 2020. He is a Distinguished Microwave

Lecturer (DML) for the IEEE MTT-S for the term of 2022–2024. He was a

Distinguished Lecturer (DL) for the IEEE Solid-State Circuits Society (SSCS)

for the term of 2018–2019. He served as the Chair of the Atlanta’s IEEE

CAS/SSCS joint chapter that won the IEEE SSCS Outstanding Chapter Award

in 2014.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 5, MAY 2022 1257

A 5G FR2 Power-Ampliﬁer With an Integrated

Power-Detector for Closed-Loop EIRP Control

Venumadhav Bhagavatula , Member, IEEE, Fan Zhang, Chechun Kuo, Anirban Sarkar, Member, IEEE,

Ashutosh Verma

, Tienyu Chang, Xiaohua Yu, Dae-Young Yoon, Ivan Siu-Chuang Lu, Member, IEEE,

Sang Won Son, Member, IEEE, and Thomas Byunghak Cho

, Fellow, IEEE

Abstract—A ﬁfth-generation (5G) frequency range 2 (FR2)

transmitter front end with a fully integrated power detector

for enabling closed-loop power control is presented. The power

detection path includes a miniature broad-side directional cou-

pler, a sense pair, and a current-mode successive approximation

analog-to-digital converter. The stacked power ampliﬁer (PA)

implemented in a 28-nm CMOS silicon on insulator (SOI) process

delivers 12.5-dBm output power with a power-added efﬁciency

of 10% and an error vector magnitude (EVM) lower than

−25 dB with a CP-OFDM/64-QAM/400-MHz bandwidth signal.

The PA supports 5G frequency bands n257/n258/n261 covering

a frequency range from 24.25 to 29.5 GHz. With a matched

output load, the power detector has less than ±0.15-dB error

over a 15-dB power dynamic range and 85

◦

temperature range.

Index Terms— Closed-loop power control (CLPC), directional

coupler, ﬁfth generation (5G), millimeter-wave (mm-wave), power

ampliﬁer (PA), power detector, successive-approximation regis-

ter (SAR) analog-to-digital converter (ADC).

I. INTRODUCTION

HE ﬁfth -generation (5G) of mobile communication is

opening the door for high-speed and low-latency wireless

data links in smartphones. To relieve the spectral congestio n

in the sub-6-GHz frequency range—occupied by long-term

evolution (LTE), Wi-Fi, UWB, Bluetooth, and a plethora

of wireless links—5G frequency range 2 (FR2) extends

cellular communication to the millimeter-wave (mm-wave)

frequencies from 24 to 52.6 GHz. The ﬁrst set of bands

that will be commercialized includes n257 (26.5–29.5 GHz),

n258 (24.25–27.5 GHz), n261 (27.5–28.35 GHz), and n260

(37–40 GHz) [1].

In advanced technology nodes, the high transistor unity

power-gain frequency (F

MAX

) has relaxed the barrier in imple-

menting single-chip integrated radios compared to the early

days of mm-wave CMOS [2]. Integrating the power ampli-

ﬁer (PA) o n the same chip has always been a challenge due

Manuscript receiv e d September 12, 2021; re vised December 2, 2021 and

January 13, 2022; accepted January 14, 2022. Date of publication

February 15, 2022; date of current version April 25, 2022. This article was

approved by Associate Editor Domine Leenaerts. (Corresponding author:

Venumadhav Bhagavatula.)

Venumadhav Bhagavatula, Fan Zhang, Chechun Kuo, Anirban Sarkar,

Ashutosh Verma, Tienyu Chang, Xiaohua Yu, Ivan Siu-Chuang Lu, and Sang

Won Son are with Samsung Semiconductor, Inc., San Jose, CA 95134 USA

(e-mail: bvenum@gmail.com).

Dae-Young Yoon and Thomas Byunghak Cho are with Samsung Electronics

De vice Solutions, Hwaseong-si, Gyeonggi-do 445-330, South Korea.

Color versions of one or more ﬁgures in this article are available at

https://doi.org/10.1109/JSSC.2022.3146872.

Digital Object Identiﬁer 10.1109/JSSC.2022.3146872

Fig. 1. Block diagram of one path in the phased-array TX. In this article,

we describe the PA matching network, and the power control loop comprising

the coupler (CPL), sense pair, and SAR IADC.

to poor efﬁciency performance in CMOS. The higher F

MAX

enables improved efﬁciency, making co-integration more

attractive. With F

MAX

exceeding 200 GHz—ﬁve times higher

than the maximum channel frequency of the n260 band—it is

possible to embed the entire mm-wave transceiver chain in a

CMOS integrated circuit (IC). The state-of-the-art mm-wave

CMOS research has pushed the boundaries for higher power,

high-efﬁciency [3]–[5] PA design. In parallel, complete 5G

transceiver prototypes with excellent error-vector-magnitude

(EVM) performance have been demonstrated in [6]. However,

to achieve the holy grail of commercial 5G cellular operation,

not merely high power but accurate power control in the

handset is essential as well. In the absence of accurate power

control, the transmitter’s (TX) effective isotropic radiated

power (EIRP) and spurious emission can violate the limits

speciﬁed in [1] over large temperature variations. The second-

harmonic spurious emission is especially sensitive since its

power increases at twice the rate of EIRP.

Integrated rms power detectors have been demonstrated in

CMOS and bipolar technologies and across a broad range

of operating frequencies extending up to mm-wave [7]–[16].

This article describes the design of a 5G FR2 TX front

end [7], shown in Fig. 1, with all the associated power

detection circuitry—a directional coupler, an rms power

detector, and a current-based successive-approximation reg-

ister (SAR) analog-to-digital converter (ADC)—in tegr ated

on-chip to enable closed-loop power control (CLPC).

Power control has been extensively implemented in

sub-6-GHz radios. However, 5G FR2 brings new challenges

because the high path loss at mm-wave frequencies necessi-

tates the application of phased-array technology to enhance

the EIRP. In Section II, the challenges in CLPC unique to

See https://www.ieee.org/publications/rights/index.html for more information.

1258 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 57, NO. 5, MAY 2022

Fig. 2. Block diagram of the power control architecture in four-element

phased array with an on-chip coupler (CPL), power detector (PDET), ADC,

and MCU.

5G FR2 are introduced. The design of the PA matching

network is described in Section III. The architecture and

circuit implementation of the power control path are covered

in Section IV. Measurement results of the proto type chip are

discussed in Section V.

II. CLPC

AND CHALLENGE S

In cellular communication, the base station estimates its dis-

tance from the user equipment (UE) to determine the optimal

power transmission level (P

OPT

) the UE should operate at. The

UE must include hardware to accurately estimate the power

it is transmitting in real time to ensure that the transmitted

power (P

OUT

) is within an error tolerance (P

TOL

),where

OPT

− P

TOL

< P

OUT

< P

OPT

+ P

TOL

. (1)

The block diagram of the power detection hardware for

four elements of the phased -array TX described in this article

is presented in Fig. 2. Directional couplers (CPLR

) placed

between each PA and antenna divert a small fraction (on the

order of −20 or −30 dB) of P

OUT

to the coupled port (P

CPL

A power detector (PDET) senses P

CPL

and tran slates it to a

dc current. A current-based ADC digitizes the PDET output

to a 12-bit code OUT

[11:0]. The output of four ADCs is

combined by the microcontroller unit to estimate the EIRP.

The modem monitors EIRP

EST

and adjusts the overall gain of

the TX chain to ensure that the TX power satisﬁes (1). This

feedback mechanism is referred to as CLPC.

A. Area and Cost of the Coupler

In the phased array, each PA will not see identical loading

due to antenna-to-antenna coupling. Therefore, independent

power detection for each element is preferable. This results

in the number of couplers growing linearly with the number

of elements. To reduce the cost of external components and

Fig. 3. PDET transfer function illustrating the impact of temperature variance.

area on the m odule, all the mm-wave directional couplers and

PDETs are integrated on-chip. This work presents the design

of an 80-μm-long broadside coupler that measures the power

delivered to the antenna across a 2:1 voltage standing wave

ratio (VSWR) with an error less than ±0.5 dB.

B. Temperature Coefﬁcient of the PDET

The FR2 TX could have m ultiple (4–12) PAs d elivering

+14–15 dBm [7] simultaneously. With a 100% TX duty cycle,

it was empirically determined using an on-chip temperature

sensor that the on-chip junction temperatures could be as high

as 100

◦

C–125

◦

C. (It is important to note that the on-chip

temperature is a strong function of the thermal d issipation

characteristics of the platform, size of the ground–plane,

and presence/absence of a heat-sink.) For accurate CLPC

operation, the combined PDET + ADC transfer function—the

mapping from P

CPL,N

to OUT

[11:0]—should be temperature

invariant.

The generic transfer function of the PDET is shown in

Fig. 3. Ideally, the output of the PDET is a linear function

of P

OUT

[dBm] and is fully characterized by two variables: the

slope m and an intercept c

PDET

[V ]=mP

OUT

[dBm]+c. (2)

The issue with a temperature-dependent m and c is shown

in Fig. 3, and the power P1 is mapped to two different PDET

readout values. A one-point calibration of each PDET in the

chip is sufﬁcient to account for part-to-part variations in the

intercept c. However, the PDET must maintain a constant m

and c across the entire operating temperature. To m inimize

the temperature coefﬁcient of the PDET in this work, the

current output of the PDET is directly digitized using an

SAR current-mode ADC (IADC). The details of the design

are described in Section IV.

C. Dynamic Range

The dynamic range required for power control varies widely

across the different standards. A 3G TX is required to maintain

accurate power control over a dynamic range of 80 dB. Prior-

art PDET circuits employ analog circuits (resistors, diodes, and

logarithmic ampliﬁers [7]) to obtain the linear-to-log relation.

The extra circuit elements—log amp and bipolar transistors—

employed for this purpose increase sensitivity to temperature

variation. The power control requirement for 5G is relaxed in

剩余323页未读，继续阅读

netshell

粉丝: 11
资源: 185

2022年RFIC专题：5G与毫米波技术的创新应用

JSSC 2022.02

maven jssc

(5)在IntelliJIDEA 中使用socketTextStream监听 8888端口，获取数据。

spark streaming demo （java 1.8）

Java 3D demo

spark streaming和实时数据处理代码

springboot如何调用串口

在IDEA中使用Spark Streaming套接字数据源实现课程实时查找

javafx 结合jSerialComm的案例

vscode怎么导入jar包

spark streaming 结合kafka 精确消费一次将结果保存到redis

jssc与jdk 版本不兼容报错

用java写spark消费kafka的消息

net.wimpi.modbus.modbus依赖

jssc jar最新版本

java程序获取温湿度传感器数据代码

android stuidio 设计一个app用来连接esp8266的热点与stm32f103c8t6通信

JAVA 监听USB扫描枪数据代码

java同时控制俩个串口

最新资源