Apollo2超低功耗微控制器数据手册

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Apollo2是一款由AmbiqMicro公司设计的超低功耗微控制器家族，专注于提供极致的能源效率和高性能。这本数据手册，文档ID为DS-A2-1p2，修订版本为1.2，发布于2020年9月，详细介绍了Apollo2 Thin MCU的各种特性和功能。首先，Apollo2 MCU的特点在于其极低的供电需求。在3.3V电压下，执行程序时从闪存或RAM运行的电流小于10微安/兆赫兹，这意味着在维持高性能的同时，能显著降低能耗。而在深度睡眠模式下，当使用RTC（实时时钟）时，电流进一步降低到仅为3微安，这对于电池供电的设备来说极其关键。该微控制器搭载了一款高性能的ARM Cortex-M4处理器，可工作频率高达48MHz，支持浮点运算，具有内存保护单元(MPU)，确保了系统的稳定性和安全性。此外，还配备了一个强大的唤醒中断控制器，最多可以处理32个中断事件，提高了系统的响应速度和实时性。存储方面，Apollo2 MCU提供了丰富的选项，包括最多1MB的闪存用于存储代码和数据，以及256KB的低泄漏RAM，适合长时间保持数据和程序。为了优化数据访问性能，它还配备了16KB的2-way关联性缓存，可以提高程序运行效率。通信接口方面，Apollo2 MCU集成了一个SPI/I2C从属端口，支持SPI/I2C主从模式，便于与外部传感器和其他微控制器进行高效通信。同时，它还内置了UART（通用异步接收发送器），使得串行通信更加便捷。对于物联网应用中的无线通信，它还包括一个集成的收发器，用于实现短距离无线连接，如蓝牙或Wi-Fi的配合。除了标准的数字输入输出外，Apollo2 MCU还配备了高精度的传感器接口，包括磁力计、陀螺仪和加速度计，这些传感器均具备数字化输出，方便直接与微控制器的数字信号处理单元相连，用于环境感知和运动跟踪等应用。最后，Apollo2 MCU的典型传感器应用电路设计简洁高效，为用户提供了一个完整的平台，可以轻松集成各种传感器，构建低功耗、高性能的物联网和嵌入式系统解决方案。总结来说，Apollo2 MCUs以其卓越的低功耗性能、强大的处理能力、丰富的存储选项和集成的传感器接口，成为物联网、智能家居、穿戴设备等领域理想的选择。通过这份数据手册，开发人员可以深入理解并利用这些特性，以创新的方式打造绿色、高效的电子产品。

Apollo2 MCU Datasheet

Ultra-Low Power Apollo MCU Family

DS-A2-1p2 Page 16 of 570 2020 Ambiq Micro, Inc.

Table 183: NCR0END Register ............................................................................................134

Table 184: NCR0END Register Bits .....................................................................................134

Table 185: NCR1START Register ........................................................................................134

Table 186: NCR1START Register Bits.................................................................................134

Table 187: NCR1END Register ............................................................................................135

Table 188: NCR1END Register Bits .....................................................................................135

Table 189: DMON0 Register.................................................................................................135

Table 190: DMON0 Register Bits .........................................................................................136

Table 191: DMON1 Register.................................................................................................136

Table 192: DMON1 Register Bits .........................................................................................136

Table 193: DMON2 Register.................................................................................................136

Table 194: DMON2 Register Bits .........................................................................................137

Table 195: DMON3 Register.................................................................................................137

Table 196: DMON3 Register Bits .........................................................................................137

Table 197: IMON0 Register ..................................................................................................137

Table 198: IMON0 Register Bits...........................................................................................138

Table 199: IMON1 Register ..................................................................................................138

Table 200: IMON1 Register Bits...........................................................................................138

Table 201: IMON2 Register ..................................................................................................138

Table 202: IMON2 Register Bits...........................................................................................139

Table 203: IMON3 Register ..................................................................................................139

Table 204: IMON3 Register Bits...........................................................................................139

Table 205: CMD Register for I2C Operations.......................................................................144

Table 206: CMD Register for SPI Operations.......................................................................144

Table 207: CMD Register Field Description.........................................................................145

Table 208: IOMSTR Register Map .......................................................................................159

Table 209: FIFO Register ......................................................................................................161

Table 210: FIFO Register Bits...............................................................................................161

Table 211: FIFOPTR Register...............................................................................................162

Table 212: FIFOPTR Register Bits .......................................................................................162

Table 213: TLNGTH Register...............................................................................................162

Table 214: TLNGTH Register Bits .......................................................................................163

Table 215: FIFOTHR Register ..............................................................................................163

Table 216: FIFOTHR Register Bits.......................................................................................163

Table 217: CLKCFG Register ...............................................................................................164

Table 218: CLKCFG Register Bits........................................................................................164

Table 219: CMD Register......................................................................................................165

Table 220: CMD Register Bits ..............................................................................................165

Table 221: STATUS Register................................................................................................166

Table 222: STATUS Register Bits ........................................................................................166

Table 223: CFG Register .......................................................................................................166

Table 224: CFG Register Bits................................................................................................167

Table 225: INTEN Register...................................................................................................168

Table 226: INTEN Register Bits ...........................................................................................168

Table 227: INTSTAT Register ..............................................................................................169

Table 228: INTSTAT Register Bits.......................................................................................170

Apollo2 MCU Datasheet

Ultra-Low Power Apollo MCU Family

DS-A2-1p2 Page 17 of 570 2020 Ambiq Micro, Inc.

Table 229: INTCLR Register ................................................................................................171

Table 230: INTCLR Register Bits .........................................................................................171

Table 231: INTSET Register .................................................................................................172

Table 232: INTSET Register Bits..........................................................................................172

Table 233: Mapping of Direct Area Access Interrupts and Corresponding REGACCINTSTAT Bits

177

Table 234: I/O Interface Interrupt Control.............................................................................180

Table 235: IOSLAVE Register Map .....................................................................................188

Table 236: FIFOPTR Register...............................................................................................189

Table 237: FIFOPTR Register Bits .......................................................................................189

Table 238: FIFOCFG Register ..............................................................................................189

Table 239: FIFOCFG Register Bits .......................................................................................190

Table 240: FIFOTHR Register ..............................................................................................190

Table 241: FIFOTHR Register Bits.......................................................................................190

Table 242: FUPD Register.....................................................................................................191

Table 243: FUPD Register Bits .............................................................................................191

Table 244: FIFOCTR Register ..............................................................................................191

Table 245: FIFOCTR Register Bits .......................................................................................191

Table 246: FIFOINC Register ...............................................................................................192

Table 247: FIFOINC Register Bits........................................................................................192

Table 248: CFG Register .......................................................................................................192

Table 249: CFG Register Bits................................................................................................193

Table 250: PRENC Register ..................................................................................................193

Table 251: PRENC Register Bits...........................................................................................194

Table 252: IOINTCTL Register ............................................................................................194

Table 253: IOINTCTL Register Bits .....................................................................................194

Table 254: GENADD Register ..............................................................................................195

Table 255: GENADD Register Bits.......................................................................................195

Table 256: INTEN Register...................................................................................................195

Table 257: INTEN Register Bits ...........................................................................................195

Table 258: INTSTAT Register ..............................................................................................196

Table 259: INTSTAT Register Bits.......................................................................................196

Table 260: INTCLR Register ................................................................................................197

Table 261: INTCLR Register Bits .........................................................................................197

Table 262: INTSET Register .................................................................................................198

Table 263: INTSET Register Bits..........................................................................................198

Table 264: REGACCINTEN Register...................................................................................199

Table 265: REGACCINTEN Register Bits ...........................................................................199

Table 266: REGACCINTSTAT Register ..............................................................................199

Table 267: REGACCINTSTAT Register Bits.......................................................................200

Table 268: REGACCINTCLR Register ................................................................................200

Table 269: REGACCINTCLR Register Bits.........................................................................200

Table 270: REGACCINTSET Register.................................................................................200

Table 271: REGACCINTSET Register Bits .........................................................................201

Table 272: HOST_IER Register ............................................................................................202

Table 273: HOST_IER Register Bits.....................................................................................202

Apollo2 MCU Datasheet

Ultra-Low Power Apollo MCU Family

DS-A2-1p2 Page 18 of 570 2020 Ambiq Micro, Inc.

Table 274: HOST_ISR Register ............................................................................................203

Table 275: HOST_ISR Register Bits.....................................................................................203

Table 276: HOST_WCR Register .........................................................................................203

Table 277: HOST_WCR Register Bits..................................................................................204

Table 278: HOST_WCS Register..........................................................................................204

Table 279: HOST_WCS Register Bits ..................................................................................204

Table 280: FIFOCTRLO Register .........................................................................................205

Table 281: FIFOCTRLO Register Bits..................................................................................205

Table 282: FIFOCTRUP Register .........................................................................................205

Table 283: FIFOCTRUP Register Bits..................................................................................205

Table 284: FIFO Register ......................................................................................................206

Table 285: FIFO Register Bits...............................................................................................206

Table 286: PDM Clock Output Reference Table...................................................................210

Table 287: PDM Operating Modes and Data Formats ..........................................................211

Table 288: Digital Volume Control .......................................................................................212

Table 289: PGA_L and PGA_R Fields of the PCFG Register ..............................................213

Table 290: LPF Digital Filter Parameters..............................................................................213

Table 291: High Pass Corner Frequency as a Function of HPCUTOFF ...............................213

Table 292: PDM Register Map..............................................................................................215

Table 293: PCFG Register.....................................................................................................216

Table 294: PCFG Register Bits .............................................................................................216

Table 295: VCFG Register ....................................................................................................218

Table 296: VCFG Register Bits.............................................................................................218

Table 297: FR Register ..........................................................................................................219

Table 298: FR Register Bits...................................................................................................219

Table 299: FRD Register .......................................................................................................220

Table 300: FRD Register Bits................................................................................................220

Table 301: FLUSH Register ..................................................................................................220

Table 302: FLUSH Register Bits...........................................................................................220

Table 303: FTHR Register.....................................................................................................221

Table 304: FTHR Register Bits .............................................................................................221

Table 305: INTEN Register...................................................................................................221

Table 306: INTEN Register Bits ...........................................................................................221

Table 307: INTSTAT Register ..............................................................................................222

Table 308: INTSTAT Register Bits.......................................................................................222

Table 309: INTCLR Register ................................................................................................223

Table 310: INTCLR Register Bits .........................................................................................223

Table 311: INTSET Register .................................................................................................223

Table 312: INTSET Register Bits..........................................................................................223

Table 313: Drive Strength Control Bits.................................................................................226

Table 314: Apollo2 MCU Pad Function Mapping ................................................................227

Table 315: Pad Function Color and Symbol Code ................................................................228

Table 316: Special Pad Types................................................................................................229

Table 317: I2C Pullup Resistor Selection..............................................................................229

Table 318: IO Master 0 I2C Configuration ...........................................................................234

Table 319: IO Master 1 I2C Configuration ...........................................................................234

Apollo2 MCU Datasheet

Ultra-Low Power Apollo MCU Family

DS-A2-1p2 Page 19 of 570 2020 Ambiq Micro, Inc.

Table 320: IO Master 2 I2C Configuration ...........................................................................234

Table 321: IO Master 3 I2C Configuration ...........................................................................235

Table 322: IO Master 4 I2C Configuration ...........................................................................235

Table 323: IO Master 5 I2C Configuration ...........................................................................235

Table 324: IO Master 0 4-wire SPI Configuration ................................................................236

Table 326: IO Master 1 4-wire SPI Configuration ................................................................237

Table 325: IO Master 0 4-wire SPI nCE Configuration ........................................................237

Table 327: IO Master 1 4-wire SPI nCE Configuration ........................................................238

Table 328: IO Master 2 4-wire SPI Configuration ................................................................238

Table 329: IO Master 2 4-wire SPI nCE Configuration ........................................................239

Table 330: IO Master 3 4-wire SPI Configuration ................................................................239

Table 331: IO Master 3 4-wire SPI nCE Configuration ........................................................239

Table 332: IO Master 4 4-wire SPI Configuration ................................................................240

Table 333: IO Master 4 4-wire SPI nCE Configuration ........................................................240

Table 334: IO Master 5 4-wire SPI Configuration ................................................................241

Table 335: IO Master 5 4-wire SPI nCE Configuration ........................................................241

Table 336: IO Master 0 3-wire SPI Configuration ................................................................241

Table 337: IO Master 1 3-wire SPI Configuration ................................................................242

Table 338: IO Master 2 3-wire SPI Configuration ................................................................242

Table 339: IO Master 3 3-wire SPI Configuration ................................................................242

Table 340: IO Master 0 3-wire SPI Configuration ................................................................243

Table 341: IO Master 5 3-wire SPI Configuration ................................................................243

Table 342: IO Slave I2C Configuration.................................................................................243

Table 343: IO Slave 4-wire SPI Configuration .....................................................................244

Table 344: IO Slave 3-wire SPI Configuration .....................................................................244

Table 345: I2C Loopback ......................................................................................................244

Table 346: 3-wire SPI Loopback ...........................................................................................245

Table 347: 4-wire SPI Loopback ...........................................................................................245

Table 348: Counter/Timer Pad Configuration .......................................................................247

Table 351: UART0 RTS Configuration.................................................................................249

Table 352: UART0 CTS Configuration.................................................................................249

Table 349: UART0 TX Configuration...................................................................................249

Table 350: UART0 RX Configuration ..................................................................................249

Table 353: UART1 TX Configuration...................................................................................250

Table 354: UART1 RX Configuration ..................................................................................250

Table 355: UART1 RTS Configuration.................................................................................250

Table 356: UART1 CTS Configuration.................................................................................250

Table 359: I2S BCLK Configuration.....................................................................................252

Table 360: I2S WCLK Configuration ...................................................................................252

Table 361: I2S DAT Configuration .......................................................................................252

Table 357: PDM CLK Configuration ....................................................................................252

Table 358: PDM DATA Configuration .................................................................................252

Table 362: CLKOUT Configuration......................................................................................253

Table 363: 32kHz CLKOUT Configuration..........................................................................253

Table 364: ADC Analog Input Configuration .......................................................................253

Table 366: Voltage Comparator Reference Configuration....................................................255

Apollo2 MCU Datasheet

Ultra-Low Power Apollo MCU Family

DS-A2-1p2 Page 20 of 570 2020 Ambiq Micro, Inc.

Table 367: Voltage Comparator Input Configuration............................................................255

Table 365: ADC Trigger Input Configuration.......................................................................255

Table 368: SWO Configuration.............................................................................................256

Table 369: GPIO Register Map .............................................................................................257

Table 370: PADREGA Register ............................................................................................259

Table 371: PADREGA Register Bits.....................................................................................259

Table 372: PADREGB Register ............................................................................................261

Table 373: PADREGB Register Bits.....................................................................................262

Table 374: PADREGC Register ............................................................................................264

Table 375: PADREGC Register Bits.....................................................................................264

Table 376: PADREGD Register ............................................................................................267

Table 377: PADREGD Register Bits.....................................................................................267

Table 378: PADREGE Register ............................................................................................269

Table 379: PADREGE Register Bits .....................................................................................269

Table 380: PADREGF Register.............................................................................................272

Table 381: PADREGF Register Bits .....................................................................................272

Table 382: PADREGG Register ............................................................................................274

Table 383: PADREGG Register Bits.....................................................................................275

Table 384: PADREGH Register ............................................................................................277

Table 385: PADREGH Register Bits.....................................................................................278

Table 386: PADREGI Register..............................................................................................280

Table 387: PADREGI Register Bits ......................................................................................280

Table 388: PADREGJ Register .............................................................................................282

Table 389: PADREGJ Register Bits......................................................................................283

Table 390: PADREGK Register ............................................................................................285

Table 391: PADREGK Register Bits.....................................................................................285

Table 392: PADREGL Register ............................................................................................288

Table 393: PADREGL Register Bits .....................................................................................288

Table 394: PADREGM Register ...........................................................................................291

Table 395: PADREGM Register Bits....................................................................................291

Table 396: CFGA Register ....................................................................................................292

Table 397: CFGA Register Bits.............................................................................................293

Table 398: CFGB Register ....................................................................................................295

Table 399: CFGB Register Bits .............................................................................................295

Table 400: CFGC Register ....................................................................................................298

Table 401: CFGC Register Bits .............................................................................................298

Table 402: CFGD Register ....................................................................................................300

Table 403: CFGD Register Bits.............................................................................................301

Table 404: CFGE Register.....................................................................................................303

Table 405: CFGE Register Bits .............................................................................................304

Table 406: CFGF Register.....................................................................................................306

Table 407: CFGF Register Bits .............................................................................................307

Table 408: CFGG Register ....................................................................................................309

Table 409: CFGG Register Bits.............................................................................................310

Table 410: PADKEY Register...............................................................................................310

Table 411: PADKEY Register Bits .......................................................................................311

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Apollo2超低功耗微控制器数据手册

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