没有合适的资源?快使用搜索试试~ 我知道了~
首页基于ZYNQ-7010的FPGA开发板开发使用教程
基于ZYNQ-7010的FPGA开发板开发使用教程
需积分: 50 120 下载量 54 浏览量
更新于2024-07-17
4
收藏 66.08MB PDF 举报
ZYNQ+SOC修炼秘籍网手版知识点总结
本资源摘要信息涵盖了ZYNQ+SOC修炼秘籍网手版的主要知识点,旨在帮助读者快速了解FPGA开发板ZYNQ7010的开发使用教程。
一、FPGA基础知识
* FPGA(Field-Programmable Gate Array)是一种可编程的逻辑门阵列,允许用户根据需要编程和配置逻辑电路。
* FPGA的优势在于其灵活性、可扩展性和高性能,广泛应用于嵌入式系统、数据处理和通信等领域。
二、ZYNQ+SOC架构
* ZYNQ+SOC(System on Chip)是一种系统级芯片,集成了FPGA和处理器的功能,能够提供高性能的处理能力和灵活的编程能力。
* ZYNQ+SOC架构包括处理器、FPGA和 peripherals,能够满足不同应用场景的需求。
三、FPGA开发流程
* FPGA开发流程通常包括设计、编译、仿真、下载和测试等步骤。
* 设计阶段包括 RTL设计、网表设计和IP核设计等。
* 编译阶段包括编译、优化和映射等步骤。
* 仿真阶段包括功能仿真和时序仿真等。
* 下载阶段包括编程和配置FPGA设备等。
* 测试阶段包括功能测试和性能测试等。
四、ZYNQ+SOC开发使用教程
* ZYNQ+SOC开发使用教程涵盖了FPGA开发流程的各个方面,包括设计、编译、仿真、下载和测试等。
* 本教程还包括使用流程和程序,旨在帮助读者快速掌握ZYNQ+SOC的开发和使用。
五、版本信息
* 本资源提供了多个版本的更新记录,包括REV1.0至REV2.0等。
* 每个版本都带来了新的功能和改进,旨在提高ZYNQ+SOC的开发和使用体验。
六、常见问题和解决方案
* 本资源提供了一些常见问题和解决方案,旨在帮助读者快速解决问题和提高开发效率。
本资源摘要信息涵盖了FPGA基础知识、ZYNQ+SOC架构、FPGA开发流程、ZYNQ+SOC开发使用教程、版本信息和常见问题和解决方案等方面的知识点,旨在帮助读者快速掌握ZYNQ+SOC的开发和使用。
![](https://csdnimg.cn/release/download_crawler_static/11040943/bg10.jpg)
一二三电子
/
米联电子
www.osrc.cn
【
ZYNQ SOC
修炼秘籍】
第
15
页 共
1185
页
5.7.2 VID_OUT IP 接口信号的定义.......................................................................................... 664
5.8 FPGA 实现的用户逻辑代码........................................................................................................ 667
5.8.1 关键信号 1.......................................................................................................................... 667
5.8.2 关键信号 2.......................................................................................................................... 667
5.8.3 关键信号 3.......................................................................................................................... 668
5.8.4 部分关键代码.................................................................................................................... 668
5.9 PS 部分........................................................................................................................................... 670
5.9.1 DMA 中断函数部分分析...................................................................................................670
5.9.2 main.c 文件..........................................................................................................................675
5.10 实验效果.......................................................................................................................................677
S03_CH06_AXI_VDMA_OV7725 摄像头采集系统................................................................................ 678
6.1 为什么要用 VDMA...................................................................................................................... 678
6.1.1 什么是帧缓存.................................................................................................................... 678
6.1.2 双缓冲机制........................................................................................................................ 678
6.1.3 Zynq 硬件架构....................................................................................................................680
6.1.4 VDMA 的作用.................................................................................................................... 680
6.2 VDMA 概述................................................................................................................................... 681
6.3 VDMA 详细介绍........................................................................................................................... 682
6.3.1 接口.................................................................................................................................... 682
6.3.2 VDMA 帧存格式................................................................................................................ 683
22.3.3 读写通道工作时序.......................................................................................................... 683
6.3.4 寄存器................................................................................................................................ 684
6.3.5 帧同步选项......................................................................................................................... 690
6.3.6 Genlock 同步机制...............................................................................................................690
6.4 使用 VDMA.................................................................................................................................. 692
6.4.1 IP 核配置.............................................................................................................................692
6.4.2 软件控制流程.................................................................................................................... 693
6.5 搭建 VDMA 图像系统................................................................................................................. 694
6.5.1 构架方案图......................................................................................................................... 694
6.5.2 构 BLOCK 模块化设计方案图..........................................................................................695
6.6 PS 部分........................................................................................................................................... 695
6.6.1 main 函数............................................................................................................................ 695
6.6.2 vdma_api.c 函数..................................................................................................................697
StartTransfer 启动 VDMA 读写通道........................................................................................................ 703
6.7 测试结果........................................................................................................................................704
S03_CH07_AXI_VDMA_OV5640 摄像头采集系统................................................................................ 705
7.1 概述.................................................................................................................................................705
7.2 搭建 VDMA 图像系统................................................................................................................. 705
7.2.1 构架方案图......................................................................................................................... 705
7.2.2 构 BLOCK 模块化设计方案图..........................................................................................706
7.3 PS 部分........................................................................................................................................... 706
7.4 测试结果........................................................................................................................................708
S03_CH08_DMA_LWIP 以太网传输.........................................................................................................709
![](https://csdnimg.cn/release/download_crawler_static/11040943/bg11.jpg)
一二三电子
/
米联电子
www.osrc.cn
【
ZYNQ SOC
修炼秘籍】
第
16
页 共
1185
页
8.1 概述.................................................................................................................................................709
8.2 搭建硬件系统................................................................................................................................ 709
8.2.1 系统构架............................................................................................................................. 709
8.2.1 启用 HP 接口..................................................................................................................... 709
8.2.2 启用 PL 到 PS 的中断资源................................................................................................710
8.2.3 启动 PS 部分的以太网接口...............................................................................................710
8.2.4 时钟的设置........................................................................................................................ 710
8.2.5 DMA IP 配置......................................................................................................................711
8.2.6 GPIO 的配置....................................................................................................................... 711
8.2.7 配置 axi_ data_fifo _0.........................................................................................................712
8.2.8 设置 S_AXIS 接口..............................................................................................................712
8.2.9 地址空间映射..................................................................................................................... 713
8.3 FPGA 的发送代码......................................................................................................................... 713
8.4 PS 部分 BSP 设置..........................................................................................................................715
8.4.1 SDK 工程 BSP 设置........................................................................................................... 715
8.4.2 lwip 函数库设置................................................................................................................. 715
8.5 PS 部分程序分析...........................................................................................................................717
8.5.1 main.c 分析..........................................................................................................................717
8.5.2 AXI DMA 数据传输过程...................................................................................................720
8.6 连接测试........................................................................................................................................724
S03_CH09_DMA_4_Video_Switch 视频切换系统................................................................................... 728
9.1 概述.................................................................................................................................................728
9.2 修改 OV_Sensor_ML 摄像头采集 IP...........................................................................................728
9.3 搭建硬件系统................................................................................................................................ 730
9.3.1 系统图................................................................................................................................. 730
9.3.2 OV_Sensor_ML IP 接线图................................................................................................. 731
9.3.3 vid_in IP 的接线图..............................................................................................................732
9.3.4 DMA 和 FIFO 通路........................................................................................................... 732
9.3.5 vid_out IP 的通路................................................................................................................733
9.3.6 AXI HP 通道和 DMA 中断................................................................................................733
9.3.7 DMA IP 的设置...................................................................................................................734
9.3.8 时钟管理模块.................................................................................................................... 735
9.3.9VTC 图像时序发生模块.................................................................................................... 735
9.4 FPGA 四路输入以及图像切换源码分析.................................................................................... 735
9.4.1 按钮输入去抖代码............................................................................................................ 735
9.4.2 DMA 4 路视频输入的 FPGA 代码....................................................................................736
9.4.3 DMA 输出通道.................................................................................................................. 738
9.5 4 路视频切换 DMA C 处理源码分析.......................................................................................... 740
9.5.1 main.c 源码..........................................................................................................................740
9.5.2 dma_intr.h 源码................................................................................................................... 744
9.5.3 dma_intr.c 中断接收源码................................................................................................... 747
9.5.4 dma_intr.c 中断发送源码................................................................................................... 750
9.6 本章小结.........................................................................................................................................754
![](https://csdnimg.cn/release/download_crawler_static/11040943/bg12.jpg)
一二三电子
/
米联电子
www.osrc.cn
【
ZYNQ SOC
修炼秘籍】
第
17
页 共
1185
页
S03_CH10_DMA_4_Video_Stitch 视频拼接系统..................................................................................... 755
10.1 概述...............................................................................................................................................755
10.2 修改 OV_Sensor_ML 摄像头采集 IP.........................................................................................755
10.3 搭建硬件系统.............................................................................................................................. 757
10.3.1 系统图............................................................................................................................... 757
10.3.2 OV_Sensor_ML IP 接线图............................................................................................... 757
10.3.3 vid_in IP 的接线图........................................................................................................... 759
10.3.4 DMA 和 FIFO 通路......................................................................................................... 759
10.3.5 vid_out IP 的通路..............................................................................................................760
10.3.6 AXI HP 通道和 DMA 中断..............................................................................................760
10.3.7 DMA IP 的设置.................................................................................................................761
10.3.7 时钟管理模块.................................................................................................................. 762
10.3.8 VTC 图像时序发生模块................................................................................................. 762
10.4 FPGA 四路输入以及图像拼接源码分析..................................................................................762
10.4.1 图像常量参数.................................................................................................................. 762
10.4.2 DMA 4 路视频输入的 FPGA 代码..................................................................................763
10.4.3 DMA 输出通道................................................................................................................ 765
10.5 4 路视频切换 DMA C 处理源码分析........................................................................................ 767
10.5.4.1 main.c 源码.....................................................................................................................767
10.5.4.2 dma_intr.h 源码.............................................................................................................. 772
10.5.4.3 dma_intr.c 中断接收源码.............................................................................................. 775
10.5.4.4 dma_intr.c 中断发送源码.............................................................................................. 778
10.6 测试结果.......................................................................................................................................782
S03_CH11_基于 TCP 的 QSPI Flash bin 文件网络烧写...........................................................................783
11.1 概述...............................................................................................................................................783
11.2 基本原理.......................................................................................................................................783
11.3 Bin 文件........................................................................................................................................783
11.4 QSPI Flash.................................................................................................................................... 784
11.5 驱动程序.......................................................................................................................................785
11.5.1 建立 TCP Server................................................................................................................785
11.5.2 lwip 库设置....................................................................................................................... 785
11.5.3 程序解析............................................................................................................................786
11.5.4 接收保存 BOOT.bin 文件................................................................................................787
11.5.5 烧写 QSPI Flash................................................................................................................ 787
11.5.6 TCP 调试信息输出........................................................................................................... 788
11.6 网络调试助手操作方法.............................................................................................................. 788
11.6.1 发送 bin 文件.................................................................................................................... 788
11.6.7 发送启动 Flash 烧写命令.................................................................................................789
11.7 Bin 文件更新验证........................................................................................................................791
11.8 待改进之处...................................................................................................................................791
S03_CH12_基于 UDP 的 QSPI Flash bin 文件网络烧写..........................................................................792
12.1 概述...............................................................................................................................................792
12.2 基本原理.......................................................................................................................................792
![](https://csdnimg.cn/release/download_crawler_static/11040943/bg13.jpg)
一二三电子
/
米联电子
www.osrc.cn
【
ZYNQ SOC
修炼秘籍】
第
18
页 共
1185
页
12.2.1 Bin 文件.............................................................................................................................792
12.2.2 QSPI Flash......................................................................................................................... 792
12.3 驱动程序.......................................................................................................................................792
12.3.1 main 函数.......................................................................................................................... 792
12.3.2 建立 UDP 连接......................................................................................................................... 793
12.3.3 lwip 库设置....................................................................................................................... 793
12.3.4 程序解析.......................................................................................................................... 794
12.3.5 接收保存 BOOT.bin 文件................................................................................................ 794
12.3.6 烧写 QSPI Flash................................................................................................................794
12.3.7 UDP 调试信息输出.......................................................................................................... 794
12.4 网络调试助手操作方法.............................................................................................................. 795
12.4.1 发送 bin 文件.................................................................................................................... 795
12.4.2 发送启动 Flash 烧写命令................................................................................................ 795
12.5 Bin 文件更新验证........................................................................................................................797
12.6 待改进之处.................................................................................................................................. 797
S03_CH13_ZYNQ A9 TCP UART 双核 AMP 例程.................................................................................. 798
13.1 概述...............................................................................................................................................798
13.2 基本原理.......................................................................................................................................798
13.2.1 软件中断........................................................................................................................... 798
13.2.2 共享内存通信................................................................................................................... 799
13.2.3 双核 BOOT....................................................................................................................... 799
13.3 驱动程序.......................................................................................................................................800
13.3.3 CORE0 工程......................................................................................................................800
13.4 CORE1 工程.................................................................................................................................802
13.4.1 main 函数.......................................................................................................................... 802
13.4.2 初始化软件中断............................................................................................................... 802
13.4.3 响应软件中断................................................................................................................... 802
13.4.4 共享内存数据读出........................................................................................................... 803
13.4.5 触发软件中断................................................................................................................... 803
13.5 工程创建及设置关键步骤.......................................................................................................... 803
13.6 工程调试关键步骤...................................................................................................................... 805
13.7 网络调试助手操作方法.............................................................................................................. 805
13.8 生成 BOOT.bin.............................................................................................................................807
13.9 双核 BOOT 验证..........................................................................................................................808
S03_CH14_通过 BRAM 进行 PS 和 PL 间的数据交互........................................................................... 809
14.1 概述...............................................................................................................................................809
14.2 基本原理.......................................................................................................................................809
14.3 PL 部分设计.................................................................................................................................810
14.3.1 IP 连线图...........................................................................................................................810
14.3.2 PS 配置..............................................................................................................................810
14.3.3 AXI BRAM Controller...................................................................................................... 810
14.3.4 Block Memory Generator..................................................................................................811
14.3.5 AXI GPIO.......................................................................................................................... 813
![](https://csdnimg.cn/release/download_crawler_static/11040943/bg14.jpg)
一二三电子
/
米联电子
www.osrc.cn
【
ZYNQ SOC
修炼秘籍】
第
19
页 共
1185
页
14.4 逻辑设计.......................................................................................................................................814
14.4.1 BRAM 读时序...................................................................................................................814
14.4.2 BRAM 写时序...................................................................................................................815
14.5 PS 程序设计.................................................................................................................................815
14.5.1 main 函数.......................................................................................................................... 815
14.5.2 GPIO 输入输出.................................................................................................................815
14.5.3 BRAM 数据写入...............................................................................................................816
14.5.4 BRAM 数据读出...............................................................................................................816
14.6 程序测试......................................................................................................................................817
14.7 课后习题......................................................................................................................................818
S03_CH15_EMIO 光电通信-FEP 子卡的使用..........................................................................................819
15.1 概述...............................................................................................................................................819
15.2 基本原理.......................................................................................................................................819
15.15.1 88E1512...........................................................................................................................819
15.15.2 88E1512 RGMII 接口时序.............................................................................................821
15.3 PL 部分设计.................................................................................................................................823
15.3.1 IP 连线图...........................................................................................................................823
15.3.2 ZYNQ PS 设置..................................................................................................................823
15.3.3 GMII to RGMII................................................................................................................. 824
15.3.4 时序约束.......................................................................................................................... 826
15.3.4 IO 口.................................................................................................................................. 829
15.4 PS 程序设计.................................................................................................................................830
15.4.1 LWIP 库修改.....................................................................................................................830
15.4.2 创建工程.......................................................................................................................... 835
15.5 程序测试.......................................................................................................................................838
15.5.1 电口测试........................................................................................................................... 838
15.5.2 光口测试........................................................................................................................... 839
S04_CH16 PL AXI ETH 光电网络通信..................................................................................................... 842
16.1 概述...............................................................................................................................................842
16.2 基本原理.......................................................................................................................................842
16.2.1 88E1512............................................................................................................................. 842
16.2.2 88E1512 RGMII 接口时序...............................................................................................844
16.3 PL 部分设计.................................................................................................................................847
16.3.1 IP 连线图...........................................................................................................................847
16.3.2 ZYNQ PS 设置..................................................................................................................847
16.3.3 AXI 1G/2.5G Ethernet Subsystem.................................................................................... 848
16.3.4 AXI Direct Memory Access.............................................................................................. 850
16.3.5 PL 至 PS 的中断............................................................................................................... 852
16.3.6 时序约束........................................................................................................................... 853
16.3.7 IO 口.................................................................................................................................. 857
16.4 PS 程序设计.................................................................................................................................857
16.4.1 LWIP 库修改.....................................................................................................................857
16.4.2 创建工程........................................................................................................................... 860
剩余1184页未读,继续阅读
2023-06-21 上传
2023-10-17 上传
2023-07-17 上传
2023-10-17 上传
2023-11-20 上传
2023-06-06 上传
![](https://profile-avatar.csdnimg.cn/381dcb98bd4b479890125e7bd2ea0de5_weixin_42413869.jpg!1)
weixin_42413869
- 粉丝: 1
- 资源: 1
上传资源 快速赚钱
我的内容管理 展开
我的资源 快来上传第一个资源
我的收益
登录查看自己的收益我的积分 登录查看自己的积分
我的C币 登录后查看C币余额
我的收藏
我的下载
下载帮助
![](https://csdnimg.cn/release/wenkucmsfe/public/img/voice.245cc511.png)
最新资源
- AirKiss技术详解:无线传递信息与智能家居连接
- Hibernate主键生成策略详解
- 操作系统实验:位示图法管理磁盘空闲空间
- JSON详解:数据交换的主流格式
- Win7安装Ubuntu双系统详细指南
- FPGA内部结构与工作原理探索
- 信用评分模型解析:WOE、IV与ROC
- 使用LVS+Keepalived构建高可用负载均衡集群
- 微信小程序驱动餐饮与服装业创新转型:便捷管理与低成本优势
- 机器学习入门指南:从基础到进阶
- 解决Win7 IIS配置错误500.22与0x80070032
- SQL-DFS:优化HDFS小文件存储的解决方案
- Hadoop、Hbase、Spark环境部署与主机配置详解
- Kisso:加密会话Cookie实现的单点登录SSO
- OpenCV读取与拼接多幅图像教程
- QT实战:轻松生成与解析JSON数据
安全验证
文档复制为VIP权益,开通VIP直接复制
![](https://csdnimg.cn/release/wenkucmsfe/public/img/green-success.6a4acb44.png)