IEEE Std 1149.1-2001：JTAG 测试访问端口与边界扫描架构标准

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"JTAG IEEE 1149标准，全称为‘IEEE Standard Test Access Port and Boundary-Scan Architecture’，是电气和电子工程师协会（IEEE）制定的一项测试访问端口和边界扫描架构的标准。该标准旨在帮助在集成电路内部集成电路，以支持印刷电路板组装后的测试、维护和支援。它定义了一个标准接口，通过这个接口可以传递指令和测试数据，并规定了一套测试功能，包括边界扫描寄存器，使得组件能够响应一组最小的指令集。" JTAG（Joint Test Action Group）是一种广泛应用于数字电路和嵌入式系统中的测试协议，它的核心是IEEE 1149.1标准。这个标准的制定旨在解决集成电路在生产过程中的测试难题，尤其是在PCB板级集成时的复杂性。JTAG通过提供一个统一的接口，允许外部设备对内部逻辑进行访问，进行各种测试和调试操作。在JTAG中，最重要的组件是测试访问端口（Test Access Port，TAP）和边界扫描链（Boundary-Scan Chain）。TAP是外部测试设备与芯片内部测试逻辑之间的接口，它控制一系列的控制信号，如TCK（Test Clock）、TDI（Test Data In）、TDO（Test Data Out）和TMS（Test Mode Select），这些信号用于控制测试模式和传输数据。 - TCK：测试时钟，提供了所有JTAG操作的时间基准。 - TDI：测试数据输入，用于将数据送入设备的边界扫描链。 - TDO：测试数据输出，用于从设备的边界扫描链读取数据。 - TMS：测试模式选择，用于切换设备的测试状态机。边界扫描链是一串位于设备输入/输出（I/O）引脚周围的逻辑单元，它们能够在正常操作和测试模式之间切换。在测试模式下，这些单元可以捕获并存储其相邻的I/O引脚的值，使得测试工程师可以独立于实际电路的其他部分检查这些引脚的信号。 JTAG标准不仅用于生产测试，还被广泛用于系统调试、在线编程（比如BSP - Boot Strap Programming）、故障隔离和故障诊断。例如，它可以用来检测和隔离PCB上的短路或开路问题，以及进行FPGA和微处理器的配置更新。 JTAG IEEE 1149标准是电子设计和制造中不可或缺的一部分，它简化了复杂的硬件测试流程，提高了生产效率，并且扩展到了软件调试和固件更新等多个领域。对于任何涉及集成电路和嵌入式系统的设计团队来说，理解和应用JTAG技术都是至关重要的。

IEEE

Std 1149.1-2001 IEEE STANDARD TEST ACCESS PORT AND

3.1.19 pin: The point at which connection is made between the integrated circuit and the substrate on which

it is mounted (e.g., the printed circuit board). For packaged components, this would be the package pin; for

components mounted directly on the substrate, this would be the bonding pad.

3.1.20 prime source: In the event that several vendors offer pin-for-pin compatible components, the prime

source is the vendor that introduced the component type.

3.1.21 private: A design feature intended solely for use by the component manufacturer.

3.1.22 public: A design feature, documented in the component data sheet, that may be used by purchasers

of the component.

3.1.23 reset: The establishment of an initial logic condition that can be either logic 0 or logic 1, as

determined by the context.

3.1.24 rising edge: A transition from a low to a high logic level. In positive logic, a change from logic 0 to

logic 1. Events that are specified to occur on the rising (falling) edge of a signal should be completed within

a fixed (frequency-independent) delay specified by the component supplier.

3.1.25 scan design: A design technique that introduces shift-register paths into digital electronic circuits

and thereby improves their testability.

3.1.26 scan path: The shift-register path through a circuit designed using the scan design technique.

3.1.27 second source: In the event that several vendors offer pin-for-pin compatible components, second-

source suppliers are vendors of the component other than the prime source.

3.1.28 selected test data register: A test data register is selected when it is required to operate by an

instruction supplied to the test logic.

3.1.29 signature analysis: A technique for compressing a sequence of logic values output from a circuit

under test into a small number of bits of data (signature) that, when compared to stored data, will indicate the

presence or absence of faults in the circuit.

3.1.30 stand-alone testing: A test of a component performed before it is assembled onto a board or other

substrate, for example, using Automatic Test Equipment (ATE).

3.1.31 stuck-at fault: A failure in a logic circuit that causes a signal connection to be fixed at 0 or 1 regard-

less of the operation of the circuitry that drives it.

3.1.32 system: Pertaining to the nontest function of the circuit.

3.1.33 system logic: Any item of logic that is dedicated to realizing the nontest function of the component

or is at the time of interest configured to achieve some aspect of the nontest function.

3.1.34 system pin: A component pin that feeds, or is fed from, the on-chip system logic.

3.1.35 test logic: Any item of logic that is a dedicated part of the test logic architecture or is at the time of

interest configured as a part of the test logic architecture.

3.1.36 update: Transfer of a logic value from the shift-register stage of a data register cell or an instruction

clock input in the Update-DR or Update-IR controller state, respectively.

IEEE

Std 1149.1-2001 IEEE STANDARD TEST ACCESS PORT AND

4.2.1 Specifications

Rules

a) Stored-state devices contained in the test logic shall retain their state indefinitely when the signal

applied to TCK is stopped at 0.

Recommendations

b) Since TCK inputs for many components may be controlled from a single driver, care should be

taken to ensure that the load presented by TCK is as small as possible.

Permissions

c) Stored-state devices contained in the test logic may retain their state indefinitely when the signal

applied to TCK is stopped at 1.

4.2.2 Description

The dedicated TCK input is included so that the serial test data path between components can be used

independently of component-specific system clocks, which may vary significantly in frequency from one

component to the next. It also permits shifting of test data concurrently with normal system operation of the

component. The latter facility is required to support the use of the TAP and test data registers in a design for

on-line system monitoring. The provision of an independent clock ensures that test data can be moved to or

from a chip without changing the state of the on-chip system logic. The independent clock is also essential if

boundary-scan registers are to be usable for board interconnect testing in all circumstances—including cases

where system clock signals are derived in one component for use in others.

While TCK will in many cases be driven by a free-running clock with a nominal 50% duty cycle, there may

be situations where the clock needs to stop for a period. One example is when an ATE needs to fetch test

data from backup memory (e.g., disc), since some test systems are unable to keep the clock running during

such an operation. This standard requires that TCK can be stopped at 0 indefinitely without causing any

change to the state of the test logic. While the TCK signal is stopped at 0, stored-state devices are required to

retain their state so that the test logic may continue its operation when clock operation restarts. Optionally, a

component also may allow TCK to be stopped at 1 for an indefinite period.

Many parts of the test logic perform operations in response to the rising or falling edge of TCK, as indicated

by the use of the phrase “on the rising (falling) edge of TCK.” These operations have to be completed within

a fixed (frequency-independent) delay after the occurrence of the relevant change at TCK, and this delay has

to be specified by the component supplier. Therefore, the phrase “on the rising (falling) edge of TCK”

should be interpreted as “within a specified delay after the rising (falling) edge of TCK.”

IEEE

BOUNDARY-SCAN ARCHITECTURE Std 1149.1-2001

NOTE—In many applications, the TCK signal applied to components that conform to this standard will have a duty

cycle close to 50% (i.e., the periods that the clock spends at 0 and 1 will be equal) at a given frequency. It is expected that

all propagation delays will be such that correct operation is achieved under these circumstances (50% duty cycle at a

given TCK frequency), particularly when data is being transferred between TDO of one chip and TDI of another.

4.3 Test mode select input (TMS)

The signal received at TMS is decoded by the TAP controller to control test operations.

4.3.1 Specifications

Rules

a) The signal presented at TMS shall be sampled by the test logic on the rising edge of TCK.

b) The design of the circuitry fed from TMS shall be such that an undriven input produces a logical

response identical to the application of a logic 1.

Recommendations

c) Since the TMS inputs for many components may be controlled from a single driver, care should be

taken to ensure that the load presented by TMS is as small as possible.

4.3.2 Description

Rule 4.3.1 b) is included so that the TAP controller is forced into the Test-Logic-Reset controller state in the

case of an undriven TMS pin. This ensures that normal operation of the complete design can continue with-

out interference from the test logic (see 6.3). For TTL-compatible designs, the rule may be met by including

a pull-up resistor in the component's TMS input circuitry.

Signal values presented at TMS are sampled by the test logic on the rising edge of TCK. It is expected that

the bus master (ATE, bus controller, etc.) will change the signal driven to the TMS inputs of connected

components on the falling edge of TCK. The waveforms shown elsewhere in this standard reflect this

expectation.

4.4 Test data input (TDI)

Serial test instructions and data are received by the test logic at TDI.

4.4.1 Specifications

Rules

a) The signal presented at TDI shall be sampled into the test logic on the rising edge of TCK.

b) The design of the circuitry fed from TDI shall be such that an undriven input produces a logical

response identical to the application of a logic 1.

c) When data is being shifted from TDI toward TDO, test data received at TDI shall appear without

inversion at TDO after a number of rising and falling edges of TCK determined by the length of the

instruction or test data register selected.

IEEE

Std 1149.1-2001 IEEE STANDARD TEST ACCESS PORT AND

4.4.2 Description

The data pins (TDI and TDO) provide for serial movement of test data through the circuit. The requirement

for data to be propagated from TDI to TDO without inversion is included to simplify the operation of com-

ponents compatible with this standard linked on a printed circuit board.

Values presented at TDI are clocked into the selected register (instruction or test data) on a rising edge of

TCK. It is expected that the bus master (ATE, bus controller, etc.) will change the signal driven to the TDI

input of the first component on a serial board-level path on the falling edge of TCK. The waveforms shown

elsewhere in this standard reflect this expectation.

Rule 4.4.1 b) is included so that open-circuit faults in the board-level serial test data path cause a defined

logic value to be shifted into the test logic. Note that when this constant value is shifted into the instruction

designs, this rule may be met by inclusion of a pull-up resistor in the component's TDI input circuitry.

4.5 Test data output (TDO)

TDO is the serial output for test instructions and data from the test logic defined in this standard.

4.5.1 Specifications

Rules

a) Changes in the state of the signal driven through TDO shall occur only on the falling edge of TCK.

b) The TDO driver shall be set to its inactive drive state except when the scanning of data is in progress

(see 6.2).

4.5.2 Description

To ensure race-free operation, changes on TAP inputs (TMS and TDI) are clocked into the test logic defined

by this standard on the rising edge of TCK while changes at the TAP output (TDO) occur on the falling edge

of TCK. Similarly, for test logic able to drive or receive signals from system pins (e.g., the boundary-scan

while those entering the test logic are clocked in on the rising edge (as will be discussed in 9.3).

The contents of the selected register (instruction or data) are shifted out of TDO on the falling edge of TCK.

In the illustrations given in this document, edge-operated circuit designs generally are used. For an edge-

operated implementation, note that the TDO output changes shall be delayed until the falling edge of TCK,

which can be achieved by including a flip-flop clocked by the falling edge of TCK in the TDO output buffer.

Where the registers are constructed from master and slave latches controlled by nonoverlapping clocks, the

retiming required by Rule 4.5.1 a) is an inherent feature of the design.

The ability of TDO to switch between active and inactive drive is required to allow parallel, rather than

serial, connection of board-level test data paths in cases where this is required. In TTL or CMOS technolo-

gies, for example, this requirement may be met through use of a 3-state output buffer.

4.6 Test reset input (TRST*)

The optional TRST* input provides for asynchronous initialization of the TAP controller (see 6.3).

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