SPI Operation
T25S6A
4. SPI Operation
NOR Flash Memory
NOR Flash Memory
4.1 Standard SPI Instructions
The T25S16A features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip
Select (/CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are
supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge
of SCLK.
4.2 Dual SPI Instructions
4.3 Quad SPI Instructions
5. Operation Features
5.1 Supply Voltage
5.1.1
Operating Supply Voltage
Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within
the specified [VCC(min), VCC(max)] range must be applied (see operating ranges of page 50). In
order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a
suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins.
This voltage must remain stable and valid until the end of the transmission of the instruction and,
for a Write instruction, until the completion of the internal write cycle (tW).
November 2013
Rev 2.0
10 / 60
The T25S16A supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual
I/O Fast Read” (3BH and BBH) instructions. These instructions allow data to be transferred to or
from the device at two times the rate of the standard SPI. When using the Dual SPI instruction the
SI and SO pins become bidirectional I/O pins: IO0 and IO1.
The T25S16A supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad
I/O Fast Read” (6BH, EBH) instructions. These instructions allow data to be transferred t-o or from
the device at four times the rate of the standard SPI. When using the Quad SPI instruction the SI
and SO pins become bidirectional I/O pins: IO0 and IO1, and /WP and /HOLD pins become IO2
and IO3. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2
to be set.
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