DP8384K芯片：低功耗工业级10/100Mbps以太网收发器详解

DP8384K

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DP83848T/K

1.6 STRAP OPTIONS

DP83848T/K uses many functional pins as strap options.

The values of these pins are sampled during reset and

used to strap the device into specific modes of operation.

The strap option pin assignments are defined below. The

functional pin name is indicated in parentheses.

A 2.2 kΩ resistor should be used for pull-down or pull-up

to change the default strap option. If the default option is

required, then there is no need for external pull-up or pull

down resistors. Since these pins may have alternate func-

tions after reset is deasserted, they should not be con-

nected directly to VCC or GND.

Signal Name Type Pin # Description

PHYAD0 (COL)

PHYAD1 (RXD_0)

PHYAD2 (RXD_1)

PHYAD3 (RXD_2)

PHYAD4 (RXD_3)

S, O, PU

S, O, PD

PHY ADDRESS [4:0]: The DP83848T/K provides five PHY ad-

dress pins, the state of which are latched into the PHYCTRL reg-

ister at system Hardware-Reset.

The DP83848T/K supports PHY Address strapping values 0

(<00000>) through 31 (<11111>). A PHY Address of 0 puts the

part into the MII Isolate Mode. The MII isolate mode must be se-

lected by strapping Phy Address 0; changing to Address 0 by reg-

ister write will not put the Phy in the MII isolate mode. Please refer

to section 2.3 for additional information.

PHYAD0 pin has weak internal pull-up resistor.

PHYAD[4:1] pins have weak internal pull-down resistors.

AN0 (LED_LINK)

AN1 (LED_SPEED)

S, O, PU

These input pins control the advertised operating mode of the de-

vice according to the following table. The value on these pins are

set by connecting them to GND (0) or V

(1) through 2.2 kΩ re-

sistors. These pins should NEVER be connected directly to

GND or VCC.

The value set at this input is latched into the DP83848T at Hard-

ware-Reset.

The float/pull-down status of these pins are latched into the Basic

Mode Control Register and the Auto_Negotiation Advertisement

The default for DP83848K is 11 since these pins have an internal

pull-up.

Note: AN1 (LED_SPEED) pin is not available in DP83848T

The default is 1 in DP83848T since the AN0 pin has an internal

pull-up.

AN1 AN0 Advertised Mode

0 0 10BASE-T, Half/Full-Duplex

0 1 100BASE-TX, Half/Full-Duplex

1 0 10BASE-T, Half-Duplex

100BASE-TX, Half-Duplex

1 1 10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

AN0 Advertised Mode

0 10BASE-T Half-Duplex

100BASE-TX, Half-Duplex

1 10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

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DP83848T/K

1.7 10 MB/S AND 100 MB/S PMD INTERFACE

1.8 SPECIAL CONNECTIONS

1.9 POWER SUPPLY PINS

LED_CFG (CRS) S, O, PU 33 LED CONFIGURATION: This strapping option determines the

mode of operation of the LED pins. Default is Mode 1. Mode 1 and

Mode 2 can be controlled via the strap option. All modes are con-

figurable via register access.

SeeTable 4 for LED Mode Selection.

MDIX_EN (RX_ER) S, O, PU 34 MDIX ENABLE: Default is to enable MDIX. This strapping option

disables Auto-MDIX. An external pull-down will disable Auto-

MDIX mode.

Signal Name Type Pin # Description

TD-, TD+ I/O 14, 15 Differential common driver transmit output (PMD Output Pair).

These differential outputs are automatically configured to either

10BASE-T or 100BASE-TX signaling.

In Auto-MDIX mode of operation, this pair can be used as the Re-

ceive Input pair.

These pins require 3.3V bias for operation.

RD-, RD+ I/O 11, 12 Differential receive input (PMD Input Pair). These differential in-

puts are automatically configured to accept either 100BASE-TX

or 10BASE-T signaling.

In Auto-MDIX mode of operation, this pair can be used as the

Transmit Output pair.

These pins require 3.3V bias for operation.

Signal Name Type Pin # Description

RBIAS I 20 Bias Resistor Connection. A 4.87 kΩ 1% resistor should be con-

nected from RBIAS to GND.

PFBOUT O 19 Power Feedback Output. Parallel caps, 10µ F (Tantalum pre-

ferred) and 0.1µF, should be placed close to the PFBOUT. Con-

nect this pin to PFBIN1 (pin 16) and PFBIN2 (pin 30). See

Section 5.4 for proper placement pin.

PFBIN1

PFBIN2

I16

Power Feedback Input. These pins are fed with power from

PFBOUT pin. A small capacitor of 0.1µF should be connected

close to each pin.

Note: Do not supply power to these pins other than from

PFBOUT.

RESERVED I/O 8,9,10 RESERVED: These pins must be left unconnected.

Signal Name Pin # Description

IOVDD33 1, 26 I/O 3.3V Supply

IOGND 40 I/O Ground

DGND 29 Digital Ground

AVDD33 18 Analog 3.3V Supply

AGND 13, 17 Analog Ground

Signal Name Type Pin # Description

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DP83848T/K

2.0 Configuration

This section includes information on the various configura-

tion options available with the DP83848T/K. The configura-

tion options described below include:

— Auto-Negotiation

— PHY Address and LED

— Half Duplex vs. Full Duplex

— Isolate mode

— Loopback mode

—BIST

2.1 AUTO-NEGOTIATION

The Auto-Negotiation function provides a mechanism for

exchanging configuration information between two ends of

a link segment and automatically selecting the highest per-

formance mode of operation supported by both devices.

Fast Link Pulse (FLP) Bursts provide the signalling used to

communicate Auto-Negotiation abilities between two

devices at each end of a link segment. For further detail

regarding Auto-Negotiation, refer to Clause 28 of the IEEE

802.3u specification. The DP83848T/K supports four differ-

ent Ethernet protocols (10 Mb/s Half Duplex, 10 Mb/s Full

Duplex, 100 Mb/s Half Duplex, and 100 Mb/s Full Duplex),

so the inclusion of Auto-Negotiation ensures that the high-

est performance protocol will be selected based on the

advertised ability of the Link Partner. The Auto-Negotiation

function within the DP83848T can be controlled either by

internal register access or by the use of the AN0 pin.

Note: In DP83848K, the Auto-Negotiation function can be

controlled either by internal register access or by the use of

AN0 and AN1 pins.

2.1.1 Auto-Negotiation Pin Control

The state of AN0 and AN1 pins determine the specific

mode advertised by the device as given in Table 2.. The

state of AN0 and AN1 pins, upon power-up/reset, deter-

mines the state of bits [8:5] of the ANAR register.

The Auto-Negotiation function selected at power-up or

reset can be changed at any time by writing to the Basic

Mode Control Register (BMCR) at address 0x00h.

Note: DP83848T does not offer the AN1 pin. Table 2 shows

the Auto-Negotiation mode in DP83848T.

Table 1. Auto-Negotiation Modes in DP83848K

AN1 AN0 Advertised Mode

0 0 10BASE-T, Half/Full-Duplex

0 1 100BASE-TX, Half/Full-Duplex

1 0 10BASE-T, Half-Duplex

100BASE-TX, Half-Duplex

1 1 10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

Table 2. Auto-Negotiation Modes in DP83848T

AN0 Advertised Mode

0 10BASE-T Half-Duplex

100BASE-TX, Half-Duplex

1 10BASE-T, Half/Full-Duplex

100BASE-TX, Half/Full-Duplex

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