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MAXIM CONFIDENTIAL 2/12/2018
ABU Apps MAX9295 MAX9296 GMSL2-MIPI-csi_programming_guide_rev2-0.docx 5 of 21
Programming
For successful initialization it is recommended to read back each register and only update the specified
bits below.
Video Pipe Enable Register:
Each bit enables a different
video pipe.
CSI Mode Register:
0b000: 1x4 mode.
0b011: 2x2 mode.
0b110: 2x4 mode.
Lane Count Register:
In 2x4 mode:
Bits [5:4] correspond to Port
B.
Bits [1:0] correspond to Port
A.
In 1x4 mode:
Bits [5:4] correspond to the
only active port, Port B.
Lane Mapping Register 1
In 1x4 mode:
[7:6] controls D3B mapping.
[5:4] controls D2B mapping.
[3:0] are “don’t cares”.
In 2x4 mode:
[7:6] control D1A mapping.
[5:4] control D0A mapping.
[3:2] control D3A mapping.
[1:0] control D2A mapping.
Lane Mapping Register 2
In 1x4 mode:
[7:4] are “don’t cares”.
[3:2] control D1B mapping.
[1:0] control D0B mapping.
In 2x4 mode:
[7:6] control D3B mapping.
[5:4] control D2B mapping.
[3:2] control D1B mapping.
[1:0] control D0B mapping.
CSI Port Selection Register:
Bits [3:0] instruct each video
pipeline to get its data from
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