Chapter 4 Pins
16 EPSON S1D13521 Hardware Functional Specification (Rev. 0.05)
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Draft
4.2.1 Shared Host Interface
4.2.2 Host Interface
4.2.3 SDRAM Interface
Table 4-3: Shared Host Interface Pin Descriptions
Pin Name Type Pin # Cell Power
RESET_L
State
Description
RESET_L I ICS HIOVDD —
This active low input sets all internal registers to their
default states and forces all signals to their inactive
states. When unused, this pin should be connected to
HIOVDD.
For RESET_L timing details, see Section 6.3,
“RESET_L Timing” on page 31.
HIRQ O O HIOVDD L This output pin is the Host IRQ.
Table 4-4: Host Interface Pin Descriptions
Pin Name Type Pin # Cell Power
RESET_L
State
Description
HDB[15:0] IO BC HIOVDD Z
These pins are the shared command/parameter lines
15-0.
HWE_L I ICS HIOVDD — This input pin is the Write Enable signal.
HRD_L I ICS HIOVDD — This input pin is the Read Enable signal.
HCS_L I IC HIOVDD — This input pin is the Chip Select signal.
HD/C I IC HIOVDD —
This input pin selects between Command (Low) and
Parameter (High).
HRDY IO BC HIOVDD H
This active high pin is the Host interface Ready (or
WAIT) signal.
Table 4-5: SDRAM Interface Pin Descriptions
Pin Name Type Pin # Cell Power
RESET_L
State
Description
SDRADR[12:0] O OH SDRIOVDD L These output pins are the SDRAM Address pins.
SDRBA[1:0] O OH SDRIOVDD L These output pins are the SDRAM Bank Address pins.
SDRCAS# O OH SDRIOVDD H This output pin is the SDRAM CAS# pin.
SDRRAS# O OH SDRIOVDD H This output pin is the SDRAM RAS# pin.
SDRRCS# O OH SDRIOVDD L This output pin is the SDRAM CS# pin.
SDRWE# O OH SDRIOVDD H This output pin is the SDRAM WE# pin.
SDRDQM[3:0] O OH SDRIOVDD H These output pins are the SDRAM DQM pins.
SDRCKE O OH SDRIOVDD H This output pin is the SDRAM CKE pin.
SDRCLK O OH SDRIOVDD H This output pin is the SDRAM CLK pin.
SDRDAT[31:0] IO BCH SDRIOVDD L These input/output pins are the SDRAM DATA pins.
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