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首页S1D13521 Epson/E-Ink硬件功能规格说明书
本资源名为"S1D13521 Epson/E-Ink Broadsheet",由SEIKOEPSON CORPORATION发布,修订版本为0.05,属于内部保密文档。这是一份硬件功能规格说明书,主要针对Epson/E-Ink技术平台,可能用于电子墨水显示设备的研发或生产。该文档旨在提供产品的技术细节,但明确指出未经Seiko Epson书面许可,不得复制或任何形式的转印,且声明对材料中的任何不准确性概不负责。 值得注意的是,这份文档并不适用于对高度可靠性有严格要求的产品,如医疗设备。它并不构成对知识产权的许可,也不保证按照其内容制造的产品不会侵犯第三方专利或版权。此外,由于涉及日本的 Foreign Exchange and Foreign Trade Law(外汇与对外贸易法)管控的战略产品,部分技术或内容可能需要出口许可证,因此在使用时应遵循相关的法律和规定。 阅读者应确保遵守这些条款,并在实际应用时进行充分的法律咨询,以避免潜在的法律风险。对于电子墨水显示技术的专业人士和开发者来说,这份S1D13521规格书是了解和设计相关产品的重要参考资料,提供了关于硬件功能、性能参数和设计指导的关键信息。通过深入理解其中的技术参数和设计规范,用户可以优化他们的产品设计,确保符合Epson的标准和市场需求。
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Chapter 4 Pins
16 EPSON S1D13521 Hardware Functional Specification (Rev. 0.05)
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4.2.1 Shared Host Interface
4.2.2 Host Interface
4.2.3 SDRAM Interface
Table 4-3: Shared Host Interface Pin Descriptions
Pin Name Type Pin # Cell Power
RESET_L
State
Description
RESET_L I ICS HIOVDD —
This active low input sets all internal registers to their
default states and forces all signals to their inactive
states. When unused, this pin should be connected to
HIOVDD.
For RESET_L timing details, see Section 6.3,
“RESET_L Timing” on page 31.
HIRQ O O HIOVDD L This output pin is the Host IRQ.
Table 4-4: Host Interface Pin Descriptions
Pin Name Type Pin # Cell Power
RESET_L
State
Description
HDB[15:0] IO BC HIOVDD Z
These pins are the shared command/parameter lines
15-0.
HWE_L I ICS HIOVDD — This input pin is the Write Enable signal.
HRD_L I ICS HIOVDD — This input pin is the Read Enable signal.
HCS_L I IC HIOVDD — This input pin is the Chip Select signal.
HD/C I IC HIOVDD —
This input pin selects between Command (Low) and
Parameter (High).
HRDY IO BC HIOVDD H
This active high pin is the Host interface Ready (or
WAIT) signal.
Table 4-5: SDRAM Interface Pin Descriptions
Pin Name Type Pin # Cell Power
RESET_L
State
Description
SDRADR[12:0] O OH SDRIOVDD L These output pins are the SDRAM Address pins.
SDRBA[1:0] O OH SDRIOVDD L These output pins are the SDRAM Bank Address pins.
SDRCAS# O OH SDRIOVDD H This output pin is the SDRAM CAS# pin.
SDRRAS# O OH SDRIOVDD H This output pin is the SDRAM RAS# pin.
SDRRCS# O OH SDRIOVDD L This output pin is the SDRAM CS# pin.
SDRWE# O OH SDRIOVDD H This output pin is the SDRAM WE# pin.
SDRDQM[3:0] O OH SDRIOVDD H These output pins are the SDRAM DQM pins.
SDRCKE O OH SDRIOVDD H This output pin is the SDRAM CKE pin.
SDRCLK O OH SDRIOVDD H This output pin is the SDRAM CLK pin.
SDRDAT[31:0] IO BCH SDRIOVDD L These input/output pins are the SDRAM DATA pins.
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Chapter 4 Pins
S1D13521 Hardware Functional Specification (Rev. 0.05) EPSON 17
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4.2.4 SPI Master Interface for Serial Flash
4.2.5 I2C Master Interface for Thermal Sensor
Table 4-6: SPI Master Interface Pin Descriptions
Pin Name Type Pin # Cell Power
RESET_L
State
Description
SPIDCS_L O O PPIOVDD H
This output pin is the Slave Chip Select for the SPI
interface.
SPICLK O O PPIOVDD L This output pin is the Slave Clock for the SPI interface.
SPIDO O O PPIOVDD L This pin is the data output for the SPI interface.
SPIDI I IC PPIOVDD — This pin is the data input for the SPI interface.
Table 4-7: I2C Master Interface Pin Descriptions
Pin Name Type Pin # Cell Power
RESET_L
State
Description
TI2CC IO BCS PPIOVDD Z
This input/output pin is the I2C Master Serial Clock.
If this pin is not used, it must be connected to
PPIOVDD.
TI2CD IO BCS PPIOVDD Z
This input/output pin is the I2C Master Data.
If this pin is not used, it must be connected to
PPIOVDD.
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Chapter 4 Pins
18 EPSON S1D13521 Hardware Functional Specification (Rev. 0.05)
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4.2.6 Gate Driver Interface
4.2.7 Source Driver Interface
Table 4-8: Gate Driver Interface Pin Descriptions
Pin Name Type Pin # Cell Power
RESET_L
State
Description
GDCLK O O PIOVDD L This output pin is the clock for the Gate Driver.
GDSP O O PIOVDD H This output pin is the Gate Driver Start Pulse.
GDOE O O PIOVDD L This output pin is the output enable for the Gate Driver.
GDRL O O PIOVDD L This output pin is the Gate Driver Right or Left.
Table 4-9: Source Driver Interface Pin Descriptions
Pin Name Type Pin # Cell Power
RESET_L
State
Description
SDCLK O O PIOVDD L This output pin is the clock for the Source Driver.
SDLE O O PIOVDD L This output pin is the latch enable for the Source Driver.
SDDO[15:0] O O PIOVDD L These are the data output pins for the Source Driver.
SDCE_L[10:9] O O PIOVDD H
These output pins are the Source Driver Chip Enables
10-9.
SDCE_L[8:0] O O PIOVDD H
These output pins are the Source Driver Chip Enables
8-0.
For details on the configurability of these pins, refer to
Section 10.3.15, “Display Engine: Driver
Configurations” on page 123 (see REG[030Ch]) and
Section 6.5.2, “Interpreted Source Driver Timings” on
page 36.
SDSHR O O PIOVDD L This output pin is the Source Driver Shift Right Enable.
SDOE O O PIOVDD L
This output pin is the output enable for the Source
Driver.
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Chapter 4 Pins
S1D13521 Hardware Functional Specification (Rev. 0.05) EPSON 19
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4.2.8 Power Switches Control Interface
The power control interface signals have dual function pins.
1. Power sequence output (default power-on function)
2. 3-wire Dialog DA8590 Active Matrix Power Management IC and compatible devices
4.2.9 Display Border Power Interface
Table 4-10: Power Switches Control Interface Pin Descriptions
Pin Name Type Pin # Cell Power
RESET_L
State
Description
PWR0/
DAPWRALL
IO BC PWIOVDD L
These input/output pins have multiple functions.
• Power Control Signal 0 (PWR0). For timing details,
see
Section 6.6.1, “Power Pin Transition
Sequence for PWR[3:0]” on page 43.
• 3-wire Power All Pin output (DAPWRALL)
PWR1/DACLK IO BC PWIOVDD L
These input/output pins have multiple functions.
• Power Control Signal 1 (PWR1). For timing details,
see
Section 6.6.1, “Power Pin Transition
Sequence for PWR[3:0]” on page 43.
• 3-wire Serial Clock (DACLK)
PWR2/DADIO IO BC PWIOVDD L
These input/output pins have multiple functions.
• Power Control Signal 2 (PWR2). For timing details,
see Section 6.6.1, “Power Pin Transition
Sequence for PWR[3:0]” on page 43.
• 3-wire data tri-state input/output (DADIO)
PWR3/
DACEB
IO BC PWIOVDD L
These input/output pins have multiple functions.
• Power Control Signal 3 (PWR3). For timing details,
see
Section 6.6.1, “Power Pin Transition
Sequence for PWR[3:0]” on page 43.
• 3-wire active low enable (DACEB)
PWRCOM O O PWIOVDD L
Display Common Power Signals. For timing details, see
Section 6.6.2, “Power Pin Transition Sequence for
PWRCOM” on page 44.
Table 4-11: Display Border Power Interface Pin Descriptions
Pin Name Type Pin # Cell Power
RESET_L
State
Description
BDR[3:0] O O PWIOVDD L
These output pins are the Display Border Power
Signals.
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Chapter 4 Pins
20 EPSON S1D13521 Hardware Functional Specification (Rev. 0.05)
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4.2.10 Miscellaneous
Table 4-12: Miscellaneous Pin Descriptions
Pin Name Type Pin # Cell Power
RESET_L
State
Description
CLKI I ICS HIOVDD —
This pin is the clock input. For details on the clock
structure, see
Section Chapter 7, “Clocks” on page 45.
OSCI I ILTR OSCVDD —
This pin is the input for the 2-terminal crystal interface.
When the internal oscillator is not used, this pin must be
connected to OSCVDD. For details on the clock
structure, see
Section Chapter 7, “Clocks” on page 45.
OSCO O OLTR OSCVDD H
This pin is the output for the 2-terminal crystal interface.
When the internal oscillator is not used, this pin must be
left unconnected. For details on the clock structure, see
Section Chapter 7, “Clocks” on page 45.
CNF[3:0] I IC HIOVDD —
These input pins are used for configuring the S1D13521
and must be connected to either HIOVDD or VSS. The
states of these pins are latched at RESET_L. For a sum
mary of configuration options, see
Section 4.3,
“Configuration Pins” on page 22.
GPIO[1:0] IO BCD2 HIOVDD Z These are the General Purpose Input/Output pins.
TESTEN I ICD2 HIOVDD —
This input pin is the Test Enable pin and is used for
production test only. This pin should be left
unconnected for normal operation.
SCANEN I ICD2 HIOVDD —
This input pin is the Scan Enable pin and is used for
production test only. This pin should be left
unconnected for normal operation.
VCP O OLTR PLLVDD —
This output pin is for production test only and must be
left unconnected for normal operation.
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