PCI Express CEM 1.1电气规范文档概述

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PCI Express (PCIe)是一种高速串行总线接口，旨在替代并扩展传统的PCI和PCI-X接口。PCIe提供了更高的带宽和更好的性能，广泛应用在各种计算机和电子设备中。本文主要介绍了PCI Express Card Electromechanical Specification Revision 1.1（PCIe CEM 1.1）电气规范文档。该规范是PCI-SIG（PCI Special Interest Group）组织发布的，定于2005年1月24日。 PCIe CEM 1.1是PCIe接口的一个重要规范，主要涉及电气特性、机械尺寸、插槽布局、信号定义等方面的内容。该规范的目的是确保不同厂商制造的PCIe设备能够互相兼容，并能在各种主板和系统中正常运行。 PCI Express电气规范文档主要包括以下内容： 1. 版本历史：PCIe CEM 1.1是从之前的版本逐步更新而来的。最初版本是1.0，于2002年7月22日发布。之后的1.0a版本在2003年4月15日发布，它纳入了工作组提出的修正意见，并修复了一些错误。最后的1.1版本于2005年3月28日发布，纳入了经过批准的修正意见和工程变更通告。 2. 电气特性：PCIe CEM 1.1规范定义了PCIe接口的电气特性。其中包括信号电平、时序要求、数据传输速率等方面的内容。这些规定确保了PCIe接口能够支持高速数据传输，并能在各种环境下正常工作。 3. 机械尺寸：PCIe CEM 1.1规范规定了PCIe卡的机械尺寸。包括卡片的长度、宽度和高度等方面的参数。这些规定确保了PCIe卡能够正确插入和固定在主板的插槽中，并且能够与其他设备和外壳兼容。 4. 插槽布局：PCIe CEM 1.1规范定义了PCIe插槽的布局。包括插槽的位置、形状和尺寸等方面的内容。这些规定确保了PCIe卡能够正确插入和固定在主板的插槽中，并且能够与其他设备和外壳兼容。 5. 信号定义：PCIe CEM 1.1规范根据不同的信号类型，定义了PCIe接口的信号定义。包括时钟、数据、控制和电源等方面的定义。这些规定确保了PCIe设备之间的正确通信和数据传输。总之，PCI Express Card Electromechanical Specification Revision 1.1是一份重要的规范文档，定义了PCIe接口的电气特性、机械尺寸、插槽布局、信号定义等方面的内容。该规范的发布旨在确保不同厂商制造的PCIe设备之间的互操作性，并确保这些设备能够在各种主板和系统中正常工作。通过遵循PCIe CEM 1.1规范，用户可以构建出高性能和可靠的计算机系统。

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PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV 1.1

2.1.3. REFCLK AC Specifications

All specifications in Table 2-1 are to be measured using a test configuration as described in Note 11

with a circuit as shown in Figure 2-10.

Table 2-1: REFCLCK DC Specifications and AC Timing Requirements

100 MHz Input Unit Note

Symbol Parameter

Min Max

Rise Edge Rate Rising Edge Rate 0.6 4.0 V/ns 2, 3

Fall Edge Rate Falling Edge Rate 0.6 4.0 V/ns 2, 3

VIH Differential Input High Voltage +150 mV 2

VIL Differential Input Low Voltage -150 mV 2

VCROSS Absolute crossing point voltage +250 +550 mV 1,4,5

VCROSS DELTA

Variation of VCROSS over all rising

clock edges

+140 mV 1,4,9

VRB Ring-back Voltage Margin -100 +100 mV 2,12

TSTABLE Time before VRB is allowed 500 ps 2,12

TPERIOD AVG Average Clock Period Accuracy -300 +2800 ppm 2,10,13

TPERIOD ABS

Absolute Period (including Jitter

and Spread Spectrum)

9.847 10.203 ns 2,6

TCCJITTER Cycle to Cycle jitter 150 ps 2

VMAX Absolute Max input voltage +1.15 V 1,7

VMIN Absolute Min input voltage - 0.3 V 1,8

Duty Cycle Duty Cycle 40 60 % 2

Rise-Fall

Matching

Rising edge rate (REFCLK+) to

falling edge rate (REFCLK-)

matching

20 % 1,14

ZC-DC Clock source DC impedance 40 60

Ω

1,11

Notes:

1. Measurement taken from single ended waveform. 5

2. Measurement taken from differential waveform.

3. Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus

REFCLK-). The signal must be monotonic through the measurement region for rise and fall time.

The 300 mV measurement window is centered on the differential zero crossing. See Figure 2-8.

4. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ 10

equals the falling edge of REFCLK-. See Figure 2-4.

5. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge

is crossing. Refers to all crossing points for this measurement. See Figure 2-4.

6. Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle

jitter, relative PPM tolerance, and spread spectrum modulation. See Figure 2-7. 15

PCI EXPRESS CARD ELECTROMECHANICAL SPECIFICATION, REV 1.1

7. Defined as the maximum instantaneous voltage including overshoot. See Figure

2-4.

8. Defined as the minimum instantaneous voltage including undershoot. See Figure 2-4.

9. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-.

This is the maximum allowed variance in VCROSS for any particular system. See Figure 2-5.

10. Refer to Section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information 5

regarding PPM considerations.

11. System board compliance measurements must use the test load card described in Figure 2-10.

REFCLK+ and REFCLK- are to be measured at the load capacitors CL. Single ended probes must

be used for measurements requiring single ended measurements. Either single ended probes with

math or differential probe can be used for differential measurements. Test load C

= 2 pF. 10

12. T

STABLE

is the time the differential clock must maintain a minimum ±150 mV differential voltage after

rising/falling edges before it is allowed to droop back into the V

±100 mV differential range. See

Figure 2-9.

13. PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is

1/1,000,000

of 100.000000 MHz exactly or 100 Hz. For 300 PPM then we have a error budget of 15

100 Hz/PPM * 300 PPM = 30 kHz. The period is to be measured with a frequency counter with

measurement window set to 100 ms or greater. The ±300 PPM applies to systems that do not

employ Spread Spectrum or that use common clock source. For systems employing Spread

Spectrum there is an additional 2500 PPM nominal shift in maximum period resulting from the 0.5%

down spread resulting in a maximum average period specification of +2800 PPM 20

14. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is

measured using a ±75 mV window centered on the median cross point where REFCLK+ rising

meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the

oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be

compared to the Fall Edge Rate of REFCLK-, the maximum allowed difference should not exceed 25

20% of the slowest edge rate. See Figure 2-6.

REFCLK–

A-0437

REFCLK+

MAX

= 1.15 V

MIN

= -0.30 V

CROSS MAX

= 550 mV

CROSS MIN

= 250 mV

Figure 2-4: Single-Ended Measurement Points for Absolute Cross Point and Swing

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