BMG v8.3 www.xilinx.com 5
PG058 April 5, 2017
Chapter 1
Overview
The Block Memory Generator core uses embedded Block Memory primitives in Xilinx®
FPGAs to extend the functionality and capability of a single primitive to memories of
arbitrary widths and depths. Sophisticated algorithms within the Block Memory Generator
core produce optimized solutions to provide convenient access to memories for a wide
range of configurations.
This core has two fully independent ports that access a shared memory space. Both A and
B ports have a write and a read interface. In UltraScale™, Zynq®-7000 and 7 series FPGA
architectures, each of the four interfaces can be uniquely configured with a different data
width. When not using all four interfaces, you can select a simplified memory configuration
(for example, a Single-Port Memory or Simple Dual-Port Memory) to reduce FPGA resource
utilization.
This core is not completely backward-compatible with the discontinued legacy Single-Port
Block Memory and Dual-Port Block Memory cores; for information about the differences,
see Appendix B, Migrating and Upgrading.
Feature Summary
Features Common to the Native Interface and AXI4 BMG Cores
• Optimized algorithms for minimum block RAM resource utilization or low power
utilization
• Configurable memory initialization
• Individual Write enable per byte in UltraScale™, Zynq -7000, Kintex®-7, and Virtex®-7
devices with or without parity
• Optimized Verilog behavioral model for fast simulation times; structural simulation
models for precise simulation of memory behaviors
• Selectable operating mode per port: WRITE_FIRST, READ_FIRST, or NO_CHANGE
• Lower data widths for UltraScale™, Zynq-7000 and 7 series devices in SDP mode
• VHDL example design and demonstration test bench demonstrating the IP core design
flow, including how to instantiate and simulate it
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