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August 2013
IPUG88_01.2
2D Scaler IP Core User’s Guide
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG88_01.2, August 2013 2 2D Scaler IP Core User’s Guide
Chapter 1. Introduction .......................................................................................................................... 4
Quick Facts ........................................................................................................................................................... 4
Features ................................................................................................................................................................ 4
Release Information .............................................................................................................................................. 5
Chapter 2. Functional Description ........................................................................................................ 6
Key Concepts........................................................................................................................................................ 6
Block Diagram....................................................................................................................................................... 6
Algorithm and Supported Filter Kernels ................................................................................................................ 7
Dynamic Parameter Updating ............................................................................................................................... 7
Rounding............................................................................................................................................................... 8
Primary I/O ............................................................................................................................................................ 9
Interface Descriptions ........................................................................................................................................... 9
Video Input/Output ....................................................................................................................................... 9
Parameter Register Read/Write Interface .................................................................................................. 10
Control Signals and Timing ........................................................................................................................ 10
Chapter 3. Parameter Settings ............................................................................................................ 14
Architecture ......................................................................................................................................................... 15
Frame Dimensions ..................................................................................................................................... 15
Filter Physical Characteristics .................................................................................................................... 15
I/O Specification .................................................................................................................................................. 16
Implementation.................................................................................................................................................... 17
Chapter 4. IP Core Generation............................................................................................................. 18
Licensing the IP Core.......................................................................................................................................... 18
Getting Started .................................................................................................................................................... 18
Configuring the 2D Scaler IP Core in IPexpress ................................................................................................. 18
IPexpress-Created Files and Top-Level Directory Structure...................................................................... 20
Instantiating the Core ................................................................................................................................. 21
Running Functional Simulation .................................................................................................................. 21
Synthesizing and Implementing the Core in a Top-Level Design .............................................................. 21
Hardware Evaluation........................................................................................................................................... 22
Enabling Hardware Evaluation in Diamond................................................................................................ 22
Enabling Hardware Evaluation in ispLEVER.............................................................................................. 22
Updating/Regenerating the IP Core .................................................................................................................... 22
Regenerating an IP Core in Diamond ........................................................................................................ 22
Regenerating an IP Core in ispLEVER ...................................................................................................... 23
Chapter 5. Support Resources ............................................................................................................ 24
Lattice Technical Support.................................................................................................................................... 24
Online Forums............................................................................................................................................ 24
Telephone Support Hotline ........................................................................................................................ 24
E-mail Support ........................................................................................................................................... 24
Local Support ............................................................................................................................................. 24
Internet ....................................................................................................................................................... 24
References.......................................................................................................................................................... 24
Revision History .................................................................................................................................................. 24
Appendix A. Resource Utilization ....................................................................................................... 25
LatticeECP3 Devices .......................................................................................................................................... 25
Ordering Part Number................................................................................................................................ 25
LatticeECP2M and LatticeECP2MS Devices ...................................................................................................... 25
Ordering Part Number................................................................................................................................ 25
Table of Contents
Table of Contents
IPUG88_01.2, August 2013 3 2D Scaler IP Core User’s Guide
LatticeECP2 and LatticeECP2S Devices ............................................................................................................ 25
Ordering Part Number................................................................................................................................ 26
LatticeXP2 Devices ............................................................................................................................................. 26
Ordering Part Number................................................................................................................................ 26
© 2013 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
IPUG88_01.2, August 2013 4 2D Scaler IP Core User’s Guide
The 2D Scaler IP core converts input video frames of one size to output video frames of a different size. Its flexible
architecture supports a wide variety of scaling algorithms. The highly configurable design takes advantage of the
embedded DSP blocks available in Lattice FPGAs. A simple I/O handshake makes the core suitable for either
streaming video or bursty input video data. In-system input and output frame sizes updating is possible on a frame
basis.
Quick Facts
Table 1-1 gives quick facts about the 2D Scaler IP core.
Features
• Supports single-color, YCbCr 4:2:2, YCbCr 4:4:4 and RGB video formats
• Supports serial and parallel processing
• Dynamic parameter updating
• Supports multi-scaling algorithms
• Configurable number of filter taps for Lanczos coefficient set
• Configurable number of phases for Bicubic, Mitchell and Lanczos coefficient sets
• Configurable pixel data width
• Configurable coefficient width
• Configurable parameter bus width and separate parameter bus clock
Table 1-1. 2D Scaler IP Core Quick Facts
2D Scaler IP Core Configuration
480P to 720P
(YCbCr4:2:2, serial)
720P to 480P
(YCbCr4:2:2, parallel)
720P to 1080P
(RGB, parallel, dynamic)
Core
Requirements
FPGA Families
Supported
LatticeECP3™, LatticeECP2M™, LatticeECP2MS,
LatticeECP2™, LatticeECP2S, LatticeXP2™
Minimum Device
Required
LFE2-6E LFE3-17EA LFE2-6E LFE3-17EA LFE2-12E LFE3-17EA
Resource
Utilization
Targeted Device
LFE2-20E-
7F484C
LFE3-17EA-
8FN484C
LFE2-20E-
7F484C
LFE3-17EA-
8FN484C
LFE2-20E-
7F484C
LFE3-17EA-
8FN484C
Taps 4x4 4x4 4x4
Pixel width 8 8 8
Coefficient width 9 9 9
Registers 953 955 1116 1113 1515
1522
LUTs 1278 1343 1267 1338 1715
1829
EBRs 4 4 7 7 9
9
MULT9x9 8 8 161624
24
Design Tool
Support
Lattice
Implementation
Lattice Diamond
®
1.3 or ispLEVER
®
8.1
Synthesis Synopsys
®
Synplify™ Pro for Lattice E-2011.03L
Simulation
Aldec
®
Active-HDL™ 8.2 Lattice Edition
Mentor Graphics
®
ModelSim™ SE 6.3F
Chapter 1:
Introduction
Introduction
IPUG88_01.2, August 2013 5 2D Scaler IP Core User’s Guide
• Selectable memory type for line buffer and coefficient memories
• Option for sharing vertical and horizontal filter coefficient memories
Release Information
• 2D Scaler IP Core version 2.0; last updated September 2, 2011
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