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Xilinx_Answer_71435_XDMA_Debug_Guide.pdf
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此文档是xilinx的dma的寄存器详细介绍,为英文文档,对xilinx的dma寄存器介绍的比较详细,有需要的可以下载。
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© Copyright 2018 Xilinx
Xilinx Answer 71435 – Driver and XDMA IP Debug Guide 1
Xilinx Answer 71435
DMA Subsystem for PCI Express - Driver and IP Debug Guide
Important Note: This downloadable PDF of an Answer Record is provided to enhance its usability and readability.
It is important to note that Answer Records are Web-based content that are frequently updated as new information becomes
available. You are reminded to visit the Xilinx Technical Support Website and review (Xilinx Answer 71435) for the latest
version of this Answer.
Introduction
The Xilinx PCI Express DMA (XDMA) IP provides high performance Scatter Gather (SG) direct memory access (DMA) via
PCI Express. Using the IP and the associated drivers and software one will be able to generate high throughput PCIe
memory transactions between a host PC and a Xilinx FPGA.
This document provides tips and techniques for debugging XDMA IP issues. As an introduction, an overview of the XDMA
architecture is provided along with its working mechanism. For more details, users are advised to check XDMA IP product
guide (PG195).
At the end of this document, the details on how the XDMA IP legacy drivers, provided in (Xilinx Answer 65444), work has
been described. The section has been introduced to provide users with the knowledge of the working mechanism of the
drivers. If an advanced debugging is required, it is advised to add printf statements at different points in the provided driver
source to narrow down the source of the issue.
DMA Architecture and Overview
The XDMA IP consists of the following interfaces as shown in Figure 1:
User Data Interface
o AXI-MM (Memory Mapped) or AXI-ST (Streaming)
Separate data port per channel in AXI-ST Interface; data port is shared between channels in the
AXI-MM interface
Up to 4 physical Read (H2C) and 4 Write (C2H) Data Channels
Each channel enabled has a dedicated engine for H2C and C2H
Descriptor module is common for all engines
Control Interfaces
o AXI-MM Lite Master Control Interface
o AXI-MM Lite Slave Control Interface accessible from user application
DMA Bypass Interface
o AXI-MM Bypass Port
Enables Host direct access to user application
User Interrupts
o Up to 16 user interrupts
© Copyright 2018 Xilinx
Xilinx Answer 71435 – Driver and XDMA IP Debug Guide 2
Status ports
o Each channel has a status port
Figure 1 - XDMA Architecture
AXI MM interface
As shown in Figure 2, the AXI MM data port is shared among the configured channels. C2H channels will master reads on
the AR bus and H2C channels will master writes on the AW bus.
Figure 2 - XDMA AXI MM Interface
© Copyright 2018 Xilinx
Xilinx Answer 71435 – Driver and XDMA IP Debug Guide 3
AXI Stream interface
When the IP is configured with the AXI Stream Interface option, each channel will have its own AXI Stream interface as
shown in Figure 3.
Figure 3 - XDMA AXI Stream Interface
Descriptor Format
Table 1 shows descriptor formats. Descriptors reside in the host memory. Each descriptor has a source address, destination
address, length, and a pointer to the next descriptor on the list unless the STOP bit is set. The Next_adjacent field indicates
how many contiguous descriptors are in the next descriptor address.
Offset
Field
Bit Index
Sub Field
Description
0x0
Magic
15:0
16'had4b. Code to verify that descriptor is valid.
Nxt_adj
5:0
The number of additional adjacent descriptors after the
descriptor located at the next descriptor address field. A
block of adjacent descriptor cannot cross a 4K boundary.
Control
4
EOP
End of packet (AXI ST C2H only)
1
Completed
Set to (1) to interrupt after the engine has completed this
descriptor. This requires global
IE_DESCRIPTOR_COMPLETED control flag set in the
SGDMA control register.
0
Stop
Set to (1) to stop the engine when it completes this
descriptor.
0x04
Len
[27:0]
Descriptor Data length
0x08 & 0x0C
Source Address
63:0
Source address for the DMA transfer
0x10 &0x14
Destination
Address
63:0
Destination address for the DMA transfer
0x18 &0x1C
Next Descriptor
Address
63:0
Address of the next descriptor in the list
© Copyright 2018 Xilinx
Xilinx Answer 71435 – Driver and XDMA IP Debug Guide 4
Table 1 – Descriptor Format (Ref: PG195)
XDMA BAR Routing
All of the requests from the host will be directed to different interfaces based on the BAR hit. Which interface corresponds
to which BAR is shown in Table 2 and Table 3. PCIe to DMA interface is always selected by default. Figure 4 shows the
routing mechanism for the incoming requests from the host when “PCIe to AXI Lite Master” and “PCIe to DMA Bypass
interfaces” are enabled.
Figure 4 - XDMA BAR Routing Mechanism
Table 2 - XDMA BAR Routing (32-bit) [Ref: PG195]
Table 3 - XDMA BAR Routing (64-bit) [Ref: PG195]
© Copyright 2018 Xilinx
Xilinx Answer 71435 – Driver and XDMA IP Debug Guide 5
Figure 5 - XDMA Interface Selection and Configuration GUI
DMA Driver
The purpose of a DMA driver that sits in the host CPU is to prepare any peripheral DMA transfers, because only the operating
system (OS) has full control over the memory system, the file system and the user space processes. First, the peripheral
device’s DMA engine is programmed with the source and destination addresses of the memory ranges to copy. Second,
the device is signaled to begin the DMA transfer and when the transfer is finished, usually, the device raises interrupts to
inform the CPU about transfers that have finished. For each interrupt, an interrupt handler, previously installed by the driver,
is called and the finished transfer can be acknowledged accordingly by the OS.
XDMA Linux Driver and Example Application
The XDMA driver provided in (Xilinx Answer 65444) consists of the following user accessible devices. The driver is provided
as a reference. It is the user’s responsibility to modify the driver to add specific requirements, or build one from scratch, as
per the need of their custom design.
xdma0_control : to access XDMA registers
xdma0_user : to access AXI-Lite Master interface
xdma0_bypass : to access DMA-Bypass interface
xdma0_h2c_0/1/2/3, xdma0_c2h_0/1/2/3 : to access each channel
There are three tests included in (Xilinx Answer 65444) which are as follows:
run_test.sh : Script to do basic transfer
o Will load driver, find out if the design is AXI-MM or AXI_ST and see how many channels are enabled.
o Will do basic transfer to all enabled channels.
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