Tetramax Tutorial.pdf

Tetramax指南文档，英文文档，用于atpg，dft设计使用。 In this tutorial, usage of Tetramax to generate test patterns will be discussed. As it is used with other tools such as VCS compiler, simulator, and Design Compiler, the scripts for their use or the basic procedures will be discussed as well. Therefore, the discussion will include:  How VCS will be used to simulate a design (Full adder) written in verilog with the help of test bench.  Test patterns will be generated for the given design  Design Compiler is used to synthesize the design using a script  Test Patterns are generated using TetraMax for the synthesized circuit.  VCS will be used to test the synthesized design whether it can pass the tests from all the patterns generated to detect faults.