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The i.MX 6ULL application processors are NXP's latest additions to a growing family of multimedia-focused products offering high-performance processing optimized for lowest power consumption. .
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i.MX 6ULL Applications Processor
Reference Manual
Document Number: IMX6ULLRM
Rev. 0, 09/2016
i.MX 6ULL Applications Processor Reference Manual, Rev. 0, 09/2016
2 NXP Semiconductors
Contents
Section number Title Page
Chapter 1
Introduction
1.1 About This Document...................................................................................................................................................147
1.1.1 Audience.................................................................................................................................................... 147
1.1.2 Organization...............................................................................................................................................147
1.1.3 Suggested Reading.....................................................................................................................................148
1.1.3.1 General Information...............................................................................................................148
1.1.3.2 Related Documentation..........................................................................................................148
1.1.4 Conventions............................................................................................................................................... 148
1.1.5 Register Access..........................................................................................................................................150
1.1.5.1 Register Diagram Field Access Type Legend........................................................................150
1.1.5.2 Register Macro Usage............................................................................................................150
1.1.6 Signal Conventions.................................................................................................................................... 152
1.1.7 Acronyms and Abbreviations.....................................................................................................................152
1.2 Introduction...................................................................................................................................................................155
1.3 Target Applications.......................................................................................................................................................155
1.4 Features.........................................................................................................................................................................155
1.5 Architectural Overview.................................................................................................................................................159
1.5.1 Simplified Block Diagram......................................................................................................................... 159
1.5.2 Architectural Partitioning...........................................................................................................................160
1.5.3 Endianness Support....................................................................................................................................162
1.5.4 Memory Interfaces..................................................................................................................................... 162
Chapter 2
Memory Maps
2.1 Memory system overview.............................................................................................................................................163
2.2 ARM Platform Memory Map....................................................................................................................................... 163
2.3 DMA memory map.......................................................................................................................................................169
Chapter 3
i.MX 6ULL Applications Processor Reference Manual, Rev. 0, 09/2016
NXP Semiconductors 3
Section number Title Page
Interrupts and DMA Events
3.1 Overview.......................................................................................................................................................................171
3.2 Cortex A7 interrupts..................................................................................................................................................... 171
3.3 SDMA event mapping.................................................................................................................................................. 175
Chapter 4
External Signals and Pin Multiplexing
4.1 Overview.......................................................................................................................................................................177
4.1.1 Muxing Options......................................................................................................................................... 177
Chapter 5
Fusemap
5.1 Boot Fusemap............................................................................................................................................................... 201
5.2 Lock Fusemap...............................................................................................................................................................212
5.3 Fusemap Descriptions Table.........................................................................................................................................212
Chapter 6
External Memory Controllers
6.1 Overview.......................................................................................................................................................................221
6.2 Multi-mode DDR controller (MMDC) overview and feature summary...................................................................... 221
6.3 EIM-PSRAM/NOR flash controller overview..............................................................................................................222
6.3.1 EIM features...............................................................................................................................................222
6.3.2 EIM boot scenarios.................................................................................................................................... 223
6.3.3 EIM boot configuration..............................................................................................................................223
6.3.4 OneNAND requirements............................................................................................................................224
Chapter 7
System Debug
7.1 Overview.......................................................................................................................................................................225
7.2 Chip and ARM Platform Debug Architecture.............................................................................................................. 225
7.2.1 Debug Features.......................................................................................................................................... 226
7.2.2 Debug system components.........................................................................................................................226
7.2.2.1 AMBA Trace Bus (ATB).......................................................................................................227
7.2.2.2 ATB replicator....................................................................................................................... 227
i.MX 6ULL Applications Processor Reference Manual, Rev. 0, 09/2016
4 NXP Semiconductors
Section number Title Page
7.2.2.3 Embedded Cross Triggering.................................................................................................. 227
7.2.2.3.1 Cross-Trigger Matrix (CTM)..........................................................................228
7.2.2.3.2 Cross-Trigger Interface (CTI).........................................................................229
7.2.2.4 Debug Access Port (DAP)..................................................................................................... 229
7.2.3 Chip-Specific SJC Features....................................................................................................................... 230
7.2.3.1 JTAG Disable Mode.............................................................................................................. 230
7.2.3.2 JTAG ID.................................................................................................................................230
7.2.4 System JTAG Controller - SJC..................................................................................................................230
7.2.5 System JTAG controller main features......................................................................................................231
7.2.6 SJC TAP Port.............................................................................................................................................231
7.2.7 SJC main blocks.........................................................................................................................................231
7.3 Smart DMA (SDMA) core............................................................................................................................................232
7.3.1 SDMA On Chip Emulation Module (OnCE) Feature Summary............................................................... 232
7.3.1.1 Other SDMA Debug Functionality........................................................................................233
7.3.1.2 SDMA ROM Patching...........................................................................................................234
7.4 Miscellaneous............................................................................................................................................................... 234
7.4.1 Clock/Reset/Power.....................................................................................................................................234
7.5 Supported tools............................................................................................................................................................. 234
Chapter 8
System Boot
8.1 Overview.......................................................................................................................................................................235
8.2 Boot modes................................................................................................................................................................... 236
8.2.1 Boot mode pin settings...............................................................................................................................237
8.2.2 High-level boot sequence...........................................................................................................................237
8.2.3 Boot From Fuses mode (BOOT_MODE[1:0] = 00b)................................................................................238
8.2.4 Serial Downloader......................................................................................................................................239
8.2.5 Internal Boot mode (BOOT_MODE[1:0] = 0b10).................................................................................... 241
8.2.6 Boot security settings.................................................................................................................................241
8.3 Device configuration.....................................................................................................................................................242
i.MX 6ULL Applications Processor Reference Manual, Rev. 0, 09/2016
NXP Semiconductors 5
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