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MPC5746C Reference Manual

Supports MPC5744B, MPC5745B, MPC5746B, MPC5744C,

MPC5745C and MPC5746C

Document Number: MPC5746CRM

Rev. 5, 10/2017

Contents

Section number Title Page

Chapter 1

About This Manual

1.1 Audience....................................................................................................................................................................... 95

1.2 Organization..................................................................................................................................................................95

1.3 Module descriptions......................................................................................................................................................95

1.3.1 Example: chip-specific information that clarifies content in the same chapter........................................... 96

1.3.2 Example: chip-specific information that refers to a different chapter......................................................... 97

1.4 Register descriptions.....................................................................................................................................................98

1.5 Conventions.................................................................................................................................................................. 99

1.5.1 Notes, Cautions, and Warnings....................................................................................................................99

1.5.2 Numbering systems......................................................................................................................................99

1.5.3 Typographic notation................................................................................................................................... 100

1.5.4 Special terms................................................................................................................................................100

Chapter 2

Introduction

2.1 Introduction...................................................................................................................................................................103

2.1.1 Target Applications......................................................................................................................................103

2.2 Block diagram...............................................................................................................................................................103

2.3 Family comparison........................................................................................................................................................104

2.4 Feature list.....................................................................................................................................................................108

2.5 Package Options............................................................................................................................................................110

2.6 Modes of Operation...................................................................................................................................................... 110

Chapter 3

Memory Map

3.1 Introduction...................................................................................................................................................................115

3.2 System memory map.....................................................................................................................................................115

3.3 NVM memory map.......................................................................................................................................................116

3.4 UTEST Memory Map...................................................................................................................................................118

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Section number Title Page

3.5 RAM memory map....................................................................................................................................................... 119

3.6 Peripheral Bridges A and B memory maps...................................................................................................................120

3.6.1 Peripheral Bridge A memory map............................................................................................................... 120

3.6.2 Peripheral Bridge B memory map............................................................................................................... 124

3.7 MC_CGM mapped peripherals memory map...............................................................................................................125

3.8 PCU mapped peripherals memory map........................................................................................................................ 126

3.9 DMAMUX mapped peripherals memory map............................................................................................................. 126

Chapter 4

Signal Description

4.1 Generic pins/balls..........................................................................................................................................................127

4.1.1 MSCR assignments......................................................................................................................................127

4.2 PAD keeping feature in LPU/STANDBY mode.......................................................................................................... 128

Chapter 5

Security Overview

5.1 Introduction...................................................................................................................................................................133

5.2 Basic security................................................................................................................................................................133

5.3 Advanced security.........................................................................................................................................................133

5.4 Detailed security information....................................................................................................................................... 134

Chapter 6

Platform Overview

6.1 Introduction...................................................................................................................................................................135

6.2 User/Privilege Access................................................................................................................................................... 136

Chapter 7

Power Management Overview

7.1 Introduction...................................................................................................................................................................139

7.1.1 Features........................................................................................................................................................ 140

7.2 Power domains..............................................................................................................................................................141

7.2.1 Power Domain0 (PD0).................................................................................................................................142

7.2.2 Power Domain1 (PD1).................................................................................................................................142

7.2.3 Power Domain2 (PD2).................................................................................................................................142

MPC5746C Reference Manual, Rev. 5, 10/2017

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Section number Title Page

7.2.4 Flash HV power domain.............................................................................................................................. 143

7.2.5 SRAM domains............................................................................................................................................143

7.2.6 SRAM Configuration...................................................................................................................................143

7.3 User operating modes, power domains, and clock gating............................................................................................ 144

7.4 Voltage regulators.........................................................................................................................................................146

7.4.1 FPREG voltage regulator.............................................................................................................................146

7.4.2 Internal regulation (Internal ballast)............................................................................................................ 148

7.4.3 LPREG voltage regulator.............................................................................................................................148

7.4.4 ULPREG voltage regulator..........................................................................................................................148

7.4.5 Flash voltage regulator.................................................................................................................................149

7.4.6 Regulation mode decoding scheme .............................................................................................................149

7.4.7 Voltage monitoring...................................................................................................................................... 150

7.4.8 Applications and Low Power Modes...........................................................................................................152

7.5 External Regulation...................................................................................................................................................... 152

7.5.1 PORST in EXTERNAL REGULATION.................................................................................................... 152

7.5.2 External regulator contol..............................................................................................................................153

7.6 Accelerated Low Power Exit........................................................................................................................................ 154

Chapter 8

Low Power Subsystem (LPU)

8.1 Introduction...................................................................................................................................................................157

8.2 Block diagram...............................................................................................................................................................157

8.3 Features.........................................................................................................................................................................158

8.4 Modes of operation....................................................................................................................................................... 160

8.5 Transition to LPU mode................................................................................................................................................161

8.6 Exit from LPU Modes...................................................................................................................................................165

8.7 Clocking........................................................................................................................................................................166

8.7.1 LPU System Clock Generation....................................................................................................................166

8.7.2 FlexCAN0 Clocking.................................................................................................................................... 168

8.7.3 LinFlexD Clocking...................................................................................................................................... 168

MPC5746C Reference Manual, Rev. 5, 10/2017

NXP Semiconductors 5