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The PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and were developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O onfiguration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
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1. General description
The PCA9554 and PCA9554A are 16-pin CMOS devices that provide 8 bits of General
Purpose parallel Input/Output (GPIO) expansion for I
2
C-bus/SMBus applications and
were developed to enhance the NXP Semiconductors family of I
2
C-bus I/O expanders.
The improvements include higher drive capability, 5 V I/O tolerance, lower supply current,
individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O
expanders provide a simple solution when additional I/O is needed for ACPI power
switches, sensors, push buttons, LEDs, fans, etc.
The PCA9554/PCA9554A consist of an 8-bit Configuration register (Input or Output
selection); 8-bit Input Port register, 8-bit Output Port register and an 8-bit Polarity
Inversion register (active HIGH or active LOW operation). The system master can enable
the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for
each input or output is kept in the corresponding Input Port or Output Port register. The
polarity of the read register can be inverted with the Polarity Inversion register. All
registers can be read by the system master. Although pin-to-pin and I
2
C-bus address
compatible with the PCF8574 series, software changes are required due to the
enhancements and are discussed in
Application Note AN469
.
The PCA9554/PCA9554A open-drain interrupt output is activated when any input state
differs from its corresponding Input Port register state and is used to indicate to the
system master that an input state has changed. The power-on reset sets the registers to
their default values and initializes the device state machine.
Three hardware pins (A0, A1, A2) vary the fixed I
2
C-bus address and allow up to eight
devices to share the same I
2
C-bus/SMBus. The PCA9554A is identical to the PCA9554
except that the fixed I
2
C-bus address is different allowing up to sixteen of these devices
(eight of each) on the same I
2
C-bus/SMBus.
2. Features
n Operating power supply voltage range of 2.3 V to 5.5 V
n 5 V tolerant I/Os
n Polarity Inversion register
n Active LOW interrupt output
n Low standby current
n Noise filter on SCL/SDA inputs
n No glitch on power-up
n Internal power-on reset
n 8 I/O pins which default to 8 inputs
n 0 Hz to 400 kHz clock frequency
PCA9554/PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
Rev. 07 — 13 November 2006 Product data sheet
PCA9554_9554A_7 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 07 — 13 November 2006 2 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
n ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per
JESD22-A115 and 1000 V CDM per JESD22-C101
n Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
n Packages offered: DIP16, SO16, SSOP16, SSOP20, TSSOP16,
HVQFN16 (2 versions: 4 × 4 × 0.85 mm and 3 × 3 × 0.85 mm), and bare die
3. Ordering information
Table 1. Ordering information
T
amb
=
−
40
°
C to +85
°
C.
Type number Topside mark Package
Name Description Version
PCA9554N PCA9554N DIP16 plastic dual in-line package; 16 leads (300 mil);
long body
SOT38-1
PCA9554AN PCA9554AN
PCA9554D PCA9554D SO16 plastic small outline package; 16 leads;
body width 7.5 mm
SOT162-1
PCA9554AD PCA9554AD
PCA9554DB 9554DB SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
PCA9554ADB 9554A
PCA9554TS PCA9554 SSOP20 plastic shrink small outline package; 20 leads;
body width 4.4 mm
SOT266-1
PCA9554ATS PA9554A
PCA9554PW 9554DH TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
PCA9554APW 9554ADH
PCA9554BS 9554 HVQFN16 plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 4 × 4 × 0.85 mm
SOT629-1
PCA9554ABS 554A
PCA9554BS3 P54 HVQFN16 plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 3 × 3 × 0.85 mm
SOT758-1
PCA9554ABS3 54A
PCA9554U - bare die - -
PCA9554_9554A_7 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 07 — 13 November 2006 3 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
4. Block diagram
All I/Os are set to inputs at reset.
Fig 1. Block diagram of PCA9554/PCA9554A
PCA9554/PCA9554A
POWER-ON
RESET
002aac492
I
2
C-BUS/SMBus
CONTROL
INPUT
FILTER
SCL
SDA
V
DD
INPUT/
OUTPUT
PORTS
IO0
V
SS
8-bit
write pulse
read pulse
IO2
IO4
IO6
IO1
IO3
IO5
IO7
LP
FILTER
V
DD
INT
A0
A1
A2
PCA9554_9554A_7 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 07 — 13 November 2006 4 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
5. Pinning information
5.1 Pinning
Fig 2. Pin configuration for DIP16 Fig 3. Pin configuration for SO16
Fig 4. Pin configuration for SSOP16 Fig 5. Pin configuration for TSSOP16
PCA9554N
PCA9554AN
A0 V
DD
A1 SDA
A2 SCL
IO0 INT
IO1 IO7
IO2 IO6
IO3 IO5
V
SS
IO4
002aac485
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
V
DD
SDA
SCL
INT
IO7
IO6
IO5
IO4
A0
A1
A2
IO0
IO1
IO2
IO3
V
SS
PCA9554D
PCA9554AD
002aac486
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
PCA9554DB
PCA9554ADB
002aac487
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
V
DD
SDA
SCL
INT
IO7
IO6
IO5
IO4
A0
A1
A2
IO0
IO1
IO2
IO3
V
SS
V
DD
SDA
SCL
INT
IO7
IO6
IO5
IO4
A0
A1
A2
IO0
IO1
IO2
IO3
V
SS
PCA9554PW
PCA9554APW
002aac488
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
PCA9554_9554A_7 © NXP B.V. 2006. All rights reserved.
Product data sheet Rev. 07 — 13 November 2006 5 of 30
NXP Semiconductors
PCA9554/PCA9554A
8-bit I
2
C-bus and SMBus I/O port with interrupt
Fig 6. Pin configuration for SSOP20
Fig 7. Pin configuration for HVQFN16
(SOT629-1)
Fig 8. Pin configuration for HVQFN16
(SOT758-1)
PCA9554TS
PCA9554ATS
INT IO7
SCL IO6
n.c. n.c.
SDA IO5
V
DD
IO4
A0 V
SS
A1 IO3
n.c. n.c.
A2 IO2
IO0 IO1
002aac489
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
002aac490
PCA9554BS
PCA9554ABS
Transparent top view
IO2
IO6
IO1 IO7
IO0 INT
A2 SCL
IO3
V
SS
IO4
IO5
A1
A0
V
DD
SDA
4 9
3 10
2 11
1 12
5
6
7
8
16
15
14
13
terminal 1
index area
002aac491
PCA9554BS3
PCA9554ABS3
Transparent top view
IO2 IO6
IO1 IO7
IO0
A2 SCL
IO3
V
SS
IO4
IO5
A1
A0
V
DD
SDA
4 9
3 10
2 11
1 12
5
6
7
8
16
15
14
13
terminal 1
index area
INT
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