Micron N25Q064A 3V Serial NOR Flash Memory: High-Speed, Quad I/O Features

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"N25Q064A是一款由Micron公司生产的串行NOR闪存记忆体，适用于3V电源，具有多种I/O功能，支持4KB扇区擦除。这款芯片提供了SPI兼容的串行总线接口，最大时钟频率可达108MHz，工作电压范围在2.7到3.6V之间。它还支持扩展SPI、双I/O和四I/O协议，可执行就地（XIP）模式，允许在上电后直接在内存中运行代码。此外，N25Q064A具备编程/擦除暂停操作，以及通过单个命令实现整个内存的连续读取功能，包括快速读取、双输出快速读取、双I/O或四I/O快速读取等。该芯片可根据应用需求灵活配置，如可调整空闲周期数和输出缓冲器配置。它还包含一个64字节的用户锁定一次性编程（OTP）区域，支持4KB子扇区擦除、64KB扇区擦除和全芯片擦除功能。为了保护数据安全，N25Q064A提供了软件和硬件写保护，软件写保护可以对每个64KB扇区进行锁定，硬件写保护则通过五个非易失性位（BP0，BP1，..." N25Q064A是Micron推出的一款高性能串行NOR闪存，其主要特点和功能包括： 1. **SPI兼容接口**：该设备采用SPI（Serial Peripheral Interface）兼容的串行总线接口，这使得它能与广泛使用的SPI控制器兼容，适合于各种嵌入式系统。 2. **高速性能**：N25Q064A的最大时钟频率为108MHz，显著提高了数据传输速率，满足高速数据处理的需求。 3. **多I/O模式**：除了基本的SPI模式，还支持双I/O和四I/O模式，最高数据传输速率可达432MHz，显著提高了读取和写入速度。 4. **执行就地（XIP）模式**：此特性允许代码直接从闪存中执行，减少了对系统RAM的依赖，从而优化了系统性能和功耗。 5. **操作灵活性**：用户可以根据应用需求配置空闲周期数量和输出缓冲器设置，以适应不同系统的读写速度要求。 6. ** OTP区域**：提供64字节的一次性编程存储空间，用于存储关键数据或固件，且一旦编程后无法更改，确保数据的安全。 7. **擦除和编程功能**：支持4KB子扇区擦除、64KB扇区擦除和全芯片擦除，这些统一大小的擦除块有利于提高编程和擦除效率。 8. **写保护机制**：软件写保护功能可通过设置易失性锁定位来防止特定扇区的数据被意外修改。同时，硬件写保护通过非易失性位定义保护区大小，增强了数据保护。 9. **低电压操作**：2.7到3.6V的工作电压范围使得该芯片适用于各种电源条件，同时也降低了功耗。 N25Q064A是一款高效、灵活且具有强大保护功能的串行NOR闪存，适合于需要高速数据传输、执行代码存储和可靠数据保护的应用场景，如嵌入式系统、物联网设备、工业控制和消费电子产品等。

Memory Map – 64Mb Density

Table 2: Sectors[127:0]

Sector Subsector

Address Range

Start End

127 2047 007F F000h 007F FFFFh

⋮ ⋮ ⋮

2032 007F 0000h 007F 0FFFh

⋮ ⋮ ⋮ ⋮

63 1023 003F F000h 003F FFFFh

⋮ ⋮ ⋮

1008 003F 0000h 003F 0FFFh

⋮ ⋮ ⋮ ⋮

0 15 0000 F000h 0000 FFFFh

⋮ ⋮ ⋮

0 0000 0000h 0000 0FFFh

64Mb, 3V, Multiple I/O Serial Flash Memory

Memory Map – 64Mb Density

PDF: 09005aef845665f4

n25q_064a_3v_65nm.pdf - Rev. N 10/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Device Protection

Table 3: Data Protection using Device Protocols

Note 1 applies to the entire table

Protection by: Description

Power-on reset and internal timer Protects the device against inadvertent data changes while the power supply is out-

side the operating specification.

Command execution check Ensures that the number of clock pulses is a multiple of one byte before executing a

PROGRAM or ERASE command, or any command that writes to the device registers.

WRITE ENABLE operation Ensures that commands modifying device data must be preceded by a WRITE ENABLE

command, which sets the write enable latch bit in the status register.

Note:

1. Extended, dual, and quad SPI protocol functionality ensures that device data is protec-

ted from excessive noise.

Table 4: Memory Sector Protection Truth Table

Note 1 applies to the entire table

Sector Lock Register

Memory Sector Protection Status

Sector Lock

Down Bit

Sector Write Lock

Bit

0 0 Sector unprotected from PROGRAM and ERASE operations. Protection status re-

versible.

0 1 Sector protected from PROGRAM and ERASE operations. Protection status rever-

sible.

1 0 Sector unprotected from PROGRAM and ERASE operations. Protection status not

reversible except by power cycle or reset.

1 1 Sector protected from PROGRAM and ERASE operations. Protection status not

reversible except by power cycle or reset.

Note:

1. Sector lock register bits are written to when the WRITE LOCK REGISTER command is exe-

cuted. The command will not execute unless the sector lock down bit is cleared (see the

WRITE LOCK REGISTER command).

Table 5: Protected Area Sizes – Upper Area

Note 1 applies to the entire table

Status Register Content Memory Content

Top/

Bottom

Bit BP3 BP2 BP1 BP0 Protected Area Unprotected Area

0 0 0 0 0 None All sectors

0 0 0 0 1 Upper 128th Sectors (0 to 126)

0 0 0 1 0 Upper 64th Sectors (0 to 125)

0 0 0 1 1 Upper 32nd Sectors (0 to 123)

0 0 1 0 0 Upper 16th Sectors (0 to119)

0 0 1 0 1 Upper 8th Sectors (0 to 111)

64Mb, 3V, Multiple I/O Serial Flash Memory

Device Protection

PDF: 09005aef845665f4

n25q_064a_3v_65nm.pdf - Rev. N 10/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Serial Peripheral Interface Modes

The device can be driven by a microcontroller while its serial peripheral interface is in

either of the two modes shown here. The difference between the two modes is the clock

polarity when the bus master is in standby mode and not transferring data. Input data is

latched in on the rising edge of the clock, and output data is available from the falling

edge of the clock.

Table 7: SPI Modes

Note 1 applies to the entire table

SPI Modes Clock Polarity

CPOL = 0, CPHA = 0 C remains at 0 for (CPOL = 0, CPHA = 0)

CPOL = 1, CPHA = 1 C remains at 1 for (CPOL = 1, CPHA = 1)

Note:

1. The listed SPI modes are supported in extended, dual, and quad SPI protocols.

Shown below is an example of three memory devices in extended SPI protocol in a sim-

ple connection to an MCU on an SPI bus. Because only one device is selected at a time,

that one device drives DQ1, while the other devices are High-Z.

Resistors ensure the device is not selected if the bus master leaves S# High-Z. The bus

master might enter a state in which all input/output is High-Z simultaneously, such as

when the bus master is reset. Therefore, the serial clock must be connected to an exter-

nal pull-down resistor so that S# is pulled HIGH while the serial clock is pulled LOW.

This ensures that S# and the serial clock are not HIGH simultaneously and that

SHCH

is met. The typical resistor value of 100kΩ, assuming that the time constant R × Cp (Cp =

parasitic capacitance of the bus line), is shorter than the time the bus master leaves the

SPI bus in High-Z.

Example: Cp = 50pF, that is R × Cp = 5μs. The application must ensure that the bus mas-

ter never leaves the SPI bus High-Z for a time period shorter than 5μs. W# and HOLD#

should be driven either HIGH or LOW, as appropriate.

64Mb, 3V, Multiple I/O Serial Flash Memory

Serial Peripheral Interface Modes

PDF: 09005aef845665f4

n25q_064a_3v_65nm.pdf - Rev. N 10/14 EN

Micron Technology, Inc. reserves the right to change products or specifications without notice.

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