![](https://csdnimg.cn/release/download_crawler_static/87783769/bg10.jpg)
55 CSI-2 Lane Allocation Table..................................................................................... 104
56 Additional CSI-2 Lane Allocation Table (TGL UP4 Only)................................................105
57 Compliance Documents.......................................................................................... 107
58 PCI Express* Signal Groups.................................................................................... 107
59 PCIe* Configurations..............................................................................................108
60 Asynchronous and Sideband Signal General Routing Guideline .................................... 110
61 CFG Signals Functionality and Termination................................................................ 114
62 Platform Clocks and Associated Signal Details and Descriptions ...................................115
63 38.4 MHz Crystal Specifications .............................................................................. 117
64 Reference Specification...........................................................................................118
65 Imaging Clock Signal Descriptions............................................................................122
66 PCH PCI Express* Signal Groups..............................................................................125
67 PCH PCI Express* Compensation Routing Guidelines ..................................................125
68 PCH PCIe* Configuration Lane Reversal Mapping........................................................126
69 SATA Reference Documents.....................................................................................127
70 SATA Compliance Documents.................................................................................. 127
71 SATA Signal Groups ...............................................................................................127
72 SATA / PCI Express* Gen 2x1 (10 Gb/s) and Gen 3 Capacitor Values ........................... 129
73 Tiger Lake Processor USB Overcurrent Pins .............................................................. 130
74 USB 3.2 Reference Documents ............................................................................... 130
75 USB 3.2 Compliance Documents ............................................................................. 131
76 USB 3.2 Gen 2x1 (10 Gb/s) Interface Signals ........................................................... 131
77 USB 3.2 Gen 1x1 (5 Gb/s) Internal Cable Differential Insertion Loss Requirements......... 132
78 Trade off of Internal Cable Loss on Margin.................................................................134
79 Example of Mobile Internal Connector Pin Assignment and Description for Two-Port
USB 3.2 Gen 2x1 (10 Gb/s).....................................................................................135
80 USB 2.0 Reference Documents ............................................................................... 137
81 USB 2.0 Compliancy Documents ............................................................................. 138
82 USB 2.0 Signal Groups (Sheet 1 of 2).......................................................................138
83 USBCOMP Routing Guidelines ................................................................................. 138
84 Example of Internal Connector Pin Assignment and Description ...................................144
85 Legacy Audio Signals .............................................................................................147
86 SoundWire* Signals............................................................................................... 149
87 GSPI Signals......................................................................................................... 150
88 eSPI Signals..........................................................................................................151
89 SPI0 Signals..........................................................................................................152
90 Reference Specifications ........................................................................................ 155
91 I
2
C* Signals..........................................................................................................155
92 Bus Capacitance Reference Chart ............................................................................ 156
93 SMBus and SMLink Signals .....................................................................................157
94 Compliance Documents.......................................................................................... 161
95 Intel
®
ME Controller Link Signals and Signal-Integrity Design Guidelines....................... 161
96 UART Signals.........................................................................................................162
97 LSx Signals...........................................................................................................162
98 Signals Required Cap or Pull-Down Resistor...............................................................163
99 Signals Recommended with Cap or Pull-down Resistor Sites.........................................163
100 Signals Required Pull-up Resistor............................................................................. 164
101 CNVio Recommended Routing Parameters ................................................................ 165
102 Power Delivery Summary for Intel
®
ME Subsystem..................................................... 170
103 Following methods can be used to trigger DnX on the platform.......................... 172
104 Intel
®
Automatic Power Switcher (Intel
®
APS) Connector..............................................177
105 Pin Location for Dual-in-Line Connector.....................................................................178
106 18-pin ZIF Connector Pinout....................................................................................199
107 Pin Location for Dual-in-Line Connector.....................................................................199
108 TSSOP-28 Pin Assignments..................................................................................... 200
Design Guide Lite—Tables
Tiger Lake UP3/UP4 Platform
Design Guide April 2020
16 Intel Confidential Doc. No.: 607872, Rev.: 1.2