Atmel XMEGA-E微控制器详细手册：全方位介绍功能与特性

需积分: 9 59 浏览量更新于2024-07-24 1 收藏 9.98MB PDF 举报

Atmel-XMEGA-E_Manual.pdf是一份详尽的Atmel AVR XMEGA E系列微控制器的数据手册，它提供了对这一高性能、低功耗和功能丰富的微控制器架构的全面描述。基于AVR增强型RISC架构，XMEGA E家族集成了多种关键模块，以满足广泛的应用需求。首先，Atmel AVRCPU是核心处理器部分，它具有先进的指令集，能够执行高效的程序逻辑，并处理复杂的计算任务。该文档详细解释了CPU的工作原理、特性以及编程接口。内存部分包括了各种存储器选项，如片内Flash、SRAM和EEPROM，这些内存用于程序存储、数据暂存和非易失性数据存储，确保了系统的可靠性和数据持久性。 EDMA (Enhanced Direct Memory Access) 是一种高速的数据传输技术，它允许CPU在不参与的情况下直接控制数据在内部和外部存储器之间的传输，提高了系统性能。事件系统支持中断和定时器管理，使得设备可以根据预设条件或外部输入触发特定的操作，增强实时响应能力。系统时钟和可选的时钟配置选项允许用户灵活调整微控制器的工作频率，适应不同应用场景的需求。电源管理和睡眠模式的设计旨在优化电池寿命，提供了多种节能状态，可以在不影响功能的前提下显著降低能耗。复位系统包括了多种类型的复位机制，确保系统在异常情况下能够正确恢复到初始状态。此外，手册还介绍了Watchdog Timer (WDT)，这是一种防止系统死锁并提供自诊断的机制。中断系统是微控制器的核心组成部分，它具备多级中断处理能力和优先级管理，能有效地处理多个并发事件，提高了系统的实时响应性和稳定性。 PORT模块提供了丰富的I/O接口，支持数字输入输出，连接外部传感器和执行器，实现设备间的数据交换。 XMEGA E还包含两个16位的TC4/5定时器/计数器，用于精确的时间测量和定时任务，以及Waveform Extension (WeX)、High-resolution Extension (Hi-Res)和Fault Extension，扩展了硬件功能，增加了测量精度和故障检测能力。 RTC (Real-Time Counter) 是一个高精度的计时器，可用于精确的时间和日期管理，支持外部同步信号。 TWI (Two-wire Serial Interface) 和 SPI (Serial Peripheral Interface) 是串行通信接口，分别支持I2C和SPI协议，方便与外部设备进行通信。 USART (Universal Synchronous Asynchronous Receiver Transmitter) 提供全双工通信，支持同步和异步模式，广泛应用于数据通信和串行接口。 IRCOM (Infrared Communication Module) 提供红外通信功能，适用于遥控、无线数据传输等应用。 XCL (XMEGA Custom Logic) 允许用户定制专用逻辑电路，增加定制化的功能和性能。 CRC (Cyclic Redundancy Check) 是一种数据校验机制，用于检测数据传输过程中的错误。最后，ADC (Analog-to-Digital Converter) 和 DAC (Digital-to-Analog Converter) 分别实现了模拟信号的数字化和数字化信号的模拟转换，这对于信号处理和模拟接口控制至关重要。 AC (Analog Comparator) 是一个比较器，用于比较两个模拟信号的大小，常用于电压检测和阈值判断。这份手册提供了关于Atmel XMEGA E微控制器所有模块的深入理解和详细设计，对于开发基于此架构的嵌入式系统项目至关重要。

XMEGA E [MANUAL]

42005C–AVR–08/2013

 Bit 7:0 – RAMPX[7:0]: Extended X-pointer Address Bits

These bits hold the MSB of the 24-bit address created by RAMPX and the 16-bit X-register. Only the number of

bits required to address the available data memory is implemented for each device. Unused bits will always read

as zero.

3.14.4 RAMPY – Extended Y-Pointer register

This register is concatenated with the Y-register for indirect addressing (LD/LDD/ST/STD) of the whole data memory

space on devices with more than 64KB of data memory. This register is not available if the data memory, including

external memory, is less than 64KB.

 Bit 7:0 – RAMPY[7:0]: Extended Y-pointer Address Bits

These bits hold the MSB of the 24-bit address created by RAMPY and the 16-bit Y-register. Only the number of

bits required to address the available data memory is implemented for each device. Unused bits will always read

as zero.

3.14.5 RAMPZ – Extended Z-Pointer register

This register is concatenated with the Z-register for indirect addressing (LD/LDD/ST/STD) of the whole data memory

space on devices with more than 64KB of data memory. RAMPZ is concatenated with the Z-register when reading

(ELPM) program memory locations above the first 64KB and writing (SPM) program memory locations above the first

128KB of the program memory.

This register is not available if the data memory, including external memory and program memory in the device, is less

than 64KB.

 Bit 7:0 – RAMPZ[7:0]: Extended Z-pointer Address Bits

These bits hold the MSB of the 24-bit address created by RAMPZ and the 16-bit Z-register. Only the number of

bits required to address the available data and program memory is implemented for each device. Unused bits will

always read as zero.

3.14.6 EIND – Extended Indirect register

This register is concatenated with the Z-register for enabling extended indirect jump (EIJMP) and call (EICALL) to the

whole program memory space on devices with more than 128KB of program memory. The register should be used for

jumps to addresses below 128KB if ECALL/EIJMP are used, and it will not be used if CALL and IJMP commands are

used. For jump or call to addresses below 128KB, this register is not used. This register is not available if the program

memory in the device is less than 128KB.

Bit 76543210

+0x0A RAMPY[7:0]

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 00000000

Bit 76543210

+0x0B RAMPZ[7:0]

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 00000000

Bit76543210

+0x0C EIND[7:0]

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 00000000

XMEGA E [MANUAL]

42005C–AVR–08/2013

 Bit 7:0 – EIND[7:0]: Extended Indirect Address Bits

These bits hold the MSB of the 24-bit address created by EIND and the 16-bit Z-register. Only the number of bits

required to access the available program memory is implemented for each device. Unused bits will always read as

zero.

3.14.7 SPL – Stack Pointer register Low

The SPH and SPL stack pointer pair represent the 16-bit SP value. The SP holds the stack pointer that points to the top

of the stack. After reset, the stack pointer points to the highest internal SRAM address. To prevent corruption when

updating the stack pointer from software, a write to SPL will automatically disable interrupts for the next four instructions

or until the next I/O memory write.

Only the number of bits required to address the available data memory, including external memory, up to 64KB is

implemented for each device. Unused bits will always read as zero.

Note: 1. Refer to specific device datasheets for exact size.

 Bit 7:0 – SP[7:0]: Stack Pointer Low Byte

These bits hold the LSB of the 16-bit stack pointer (SP).

3.14.8 SPH – Stack Pointer register High

Note: 1. Refer to specific device datasheets for the exact size.

 Bit 7:0 – SP[15:8]: Stack Pointer High Byte

These bits hold the MSB of the 16-bit stack pointer (SP).

3.14.9 SREG – Status register

The status register (SREG) contains information about the result of the most recently executed arithmetic or logic

instruction. For details information about the bits in this register and how they are affected by the different instructions

see “Instruction Set Summary” on page 424.

 Bit 7 – I: Global Interrupt Enable

The global interrupt enable bit must be set for interrupts to be enabled. If the global interrupt enable register is

cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. This bit is not

cleared by hardware after an interrupt has occurred. This bit can be set and cleared by the application with the SEI

and CLI instructions, as described in “Instruction Set Summary” on page 424. Changing the I flag through the I/O-

Bit 76543210

+0x0D SP[7:0]

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value

(1)

0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

Bit 76543210

+0x0E SP[15:8]

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value

(1)

0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1

Bit 76543210

+0x0F ITHSVNZC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value 00000000

XMEGA E [MANUAL]

42005C–AVR–08/2013

4. Memories

4.1 Features

 Flash program memory

 One linear address space

 In-system programmable

 Self-programming and boot loader support

 Application section for application code

 Application table section for application code or data storage

 Boot section for application code or bootloader code

 Separate read/write protection lock bits for all sections

 Built in fast CRC check of a selectable flash program memory section

 Data memory

 One linear address space

 Single-cycle access from CPU

 SRAM

 EEPROM

 Byte and page accessible

 Memory mapped for direct load and store

 I/O memory

 Configuration and status registers for all peripherals and modules

 4 bit-accessible general purpose registers for global variables or flags

 Bus arbitration

 Deterministic handling of priority between CPU, EDMA controller, and other bus masters

 Separate buses for SRAM, EEPROM, I/O memory, and external memory access

 Simultaneous bus access for CPU and EDMA controller

 Production signature row memory for factory programmed data

 ID for each microcontroller device type

 Serial number for each device

 Calibration bytes for factory calibrated peripherals

 User signature row

 One flash page in size

 Can be read and written from software

 Content is kept after chip erase

4.2 Overview

This section describes the different memory sections. The AVR architecture has two main memory spaces, the program

memory and the data memory. Executable code can reside only in the program memory, while data can be stored in the

program memory and the data memory. The data memory includes the internal SRAM, and EEPROM for nonvolatile

data storage. All memory spaces are linear and require no memory bank switching. Nonvolatile memory (NVM) spaces

can be locked for further write and read/write operations. This prevents unrestricted access to the application software.

A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can

only be written by an external programmer.

4.3 Flash program memory

All XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The flash memory

can be accessed for read and write from an external programmer through the PDI or from application software running in

the device.

All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized

in two main sections, the application section and the boot loader section, as shown in Figure 4-1 on page 21. The sizes

剩余438页未读，继续阅读

lanbingbixue

粉丝: 0
资源: 4

Atmel XMEGA-E微控制器详细手册：全方位介绍功能与特性

XMEGA-A3BU开发板焊接布局详析

Atmel XMEGA红外通信与cs网络验证系统源码解析

Atmel-ICE用户指南：ARM Cortex-M及AVR微控制器调试编程工具

XMEGA-D_Manual.pdf

Atmel-42330-Atmel-ICE_UserGuide.pdf

XMEGA_IR_communication_module.zip_单片机开发_C/C++_

EEPROM.rar_eeprom xmega_xmega_xmega eeprom_xmega eeprom iccavr

SPI_MASTER.rar_XMEGA1604_mega16 spi_spi avr

XMEGA-A3BUXplained评估套件入门指南.pdf

uart.rar_xmega_xmega test_xmega uart

最新资源