OUT Transactions
For an OUT transaction, the application performs the following steps:
1. Enables the endpoint
2. Waits for the packet received interrupt from the USB OTG controller
3. Retrieves the packet from the receive FIFO buffer
When an OUT token or PING token is received on an endpoint where the receive FIFO buffer does not
have sufficient space, the controller performs the following steps:
1. Generates an interrupt
2. Returns a NAK handshake to USB host
If sufficient space is available, the controller stores the data in the receive FIFO buffer and returns an ACK
handshake to the USB link.
Control Transfers
For control transfers, the application performs the following steps:
1. Waits for the packet received interrupt from the controller
2. Retrieves the packet from the receive buffer
Because the control transfer is governed by USB protocol, the controller always responds with an ACK
handshake.
USB OTG Controller Address Map and Register Definitions
The address map and register definitions for the USB OTG Controller consists of the following region:
USB OTG Controller Module Registers Address Map on page 18-16
Registers in the USB OTG Controller Module. Only the Core Global, Power and Clock Gating, Data FIFO
Access, and Host Port registers can be accessedin both Host and Device modes. When the USB OTG
Controller is operating in one mode, either Device or Host, the application must not access registers from
the other mode. If an illegal access occurs, a Mode Mismatch interrupt is generated and reflected in the
Core Interrupt register (GINTSTS.ModeMis). When the core switches from one mode to another, the
registers in the new mode must be reprogrammed as they would be after a power-on reset. The register
address map is fixed and does not depend on the module configuration (for example, how many
endpoints are implemented). Host and Device mode registers occupy different addresses.
Related Information
• Introduction to the Hard Processor System on page 1-1
The base addresses of all modules are listed in the Introduction to the Hard Processor System chapter.
• http://www.altera.com/literature/hb/cyclone-v/hps.html
USB OTG Controller Module Registers Address Map
Registers in the USB OTG Controller Module. Only the Core Global, Power and Clock Gating, Data FIFO
Access, and Host Port registers can be accessedin both Host and Device modes. When the USB OTG
Controller is operating in one mode, either Device or Host, the application must not access registers from
the other mode. If an illegal access occurs, a Mode Mismatch interrupt is generated and reflected in the
18-16
OUT Transactions
cv_5v4
2015.05.04
Altera Corporation
USB 2.0 OTG Controller
Send Feedback
剩余801页未读，继续阅读
saiweili8
- 粉丝: 1
- 资源: 2
我的内容管理
展开
最新资源
- 多模态联合稀疏表示在视频目标跟踪中的应用
- Kubernetes资源管控与Gardener开源软件实践解析
- MPI集群监控与负载平衡策略
- 自动化PHP安全漏洞检测：静态代码分析与数据流方法
- 青苔数据CEO程永：技术生态与阿里云开放创新
- 制造业转型： HyperX引领企业上云策略
- 赵维五分享：航空工业电子采购上云实战与运维策略
- 单片机控制的LED点阵显示屏设计及其实现
- 驻云科技李俊涛：AI驱动的云上服务新趋势与挑战
- 6LoWPAN物联网边界路由器：设计与实现
- 猩便利工程师仲小玉：Terraform云资源管理最佳实践与团队协作
- 类差分度改进的互信息特征选择提升文本分类性能
- VERITAS与阿里云合作的混合云转型与数据保护方案
- 云制造中的生产线仿真模型设计与虚拟化研究
- 汪洋在PostgresChina2018分享：高可用 PostgreSQL 工具与架构设计
- 2018 PostgresChina大会：阿里云时空引擎Ganos在PostgreSQL中的创新应用与多模型存储
资源上传下载、课程学习等过程中有任何疑问或建议，欢迎提出宝贵意见哦~我们会及时处理！
点击此处反馈
